EP910LI-50 vs EP910LI-20 比較
詳細並排比較 EP910LI-50 由 Altera 與 EP910LI-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LI-50 | EP910LI-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 50 ns | — |
| Package Type | CERDIP-40 (L) | Through-Hole, Ceramic DIP with Quartz Window |
| Package Pin Count | 40 | — |
| Supply Voltage (VCC) | 5 V +/- 10% | 5 V |
| 工作溫度 | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable |
| Logic Blocks | Classic AND/OR array architecture | — |
| I/O Pins | [DATA_NEEDED: I/O pin count] | 24 |
| Programming Method | EPROM programmer (UV-erasable window) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Speed Grade Suffix | -50 (50 ns tPD) | — |
| Maximum Operating Frequency | — | 62 MHz |
| Propagation Delay (tpd) | — | 20 ns |
| Dedicated Inputs | — | 16 |
| 封裝 | — | 40-pin Ceramic DIP (Windowed) |
| Temperature Grade | — | Industrial (-40C to +85C) |
| 腳位數 | — | 40 |
| Logic Family | — | EPLD (Erasable PLD) |
| Architecture | — | Sum-of-products macrocell |
| Pin/Package Compatibility | — | Pin-compatible across EP910 family |