EP910LI-50 vs EP910LI-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-50 sa pamamagitan ng Altera at EP910LI-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-50 | EP910LI-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 50 ns | — |
| Package Type | CERDIP-40 (L) | Through-Hole, Ceramic DIP with Quartz Window |
| Package Pin Count | 40 | — |
| Supply Voltage (VCC) | 5 V +/- 10% | 5 V |
| Temperature na Operasyon | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable |
| Logic Blocks | Classic AND/OR array architecture | — |
| I/O Pins | [DATA_NEEDED: I/O pin count] | 24 |
| Programming Method | EPROM programmer (UV-erasable window) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Speed Grade Suffix | -50 (50 ns tPD) | — |
| Maximum Operating Frequency | — | 62 MHz |
| Propagation Delay (tpd) | — | 20 ns |
| Dedicated Inputs | — | 16 |
| Packhaging | — | 40-pin Ceramic DIP (Windowed) |
| Temperature Grade | — | Industrial (-40C to +85C) |
| Bilang ng Pin | — | 40 |
| Logic Family | — | EPLD (Erasable PLD) |
| Architecture | — | Sum-of-products macrocell |
| Pin/Package Compatibility | — | Pin-compatible across EP910 family |