EPC8Q1100 vs EPC8QI100 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPC8Q1100 disebabkan oleh Altera dan EPC8QI100 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPC8Q1100 - 8 Mbit Enhanced Config Device for SRAM FPGAs | Altera
EPC8Q1100 ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EPC8Q1100 | EPC8QI100 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | Memory ICs |
| Status Lingkungan Hidup | Masa Terakhir Dibeli | Obsolete |
| Product Type | Enhanced Configuration Device (boot PROM) | — |
| Memory Density | 8 Mbit (8,388,608 bits) | — |
| Supported FPGAs | Altera SRAM-based LUT FPGAs (Cyclone, Stratix, APEX, ACEX, Mercury, Excalibur) | — |
| Configuration Interface | Altera Enhanced Config serial interface (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | — |
| Max DCLK Frequency | 33 MHz (Fast-mode) | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Supply Voltage (VCCIO for FPGA interface) | 1.8 V / 2.5 V / 3.3 V tolerant | — |
| Programming Interface | IEEE Std 1149.1 JTAG (ISP) + serial byte-blaster mode | — |
| In-System Programmable | Yes | — |
| Kemasan | 100-pin PQFP (plastic quad flat pack) | 100-PQFP (20 x 14 mm) |
| Suhu Operasi | -40 C to +85 C (industrial) | -40C to +85C (industrial) |
| Operating Current (active read) | [DATA_NEEDED: active ICC] | — |
| Standby Current | [DATA_NEEDED: ICC standby] | — |
| Endurance (program/erase cycles) | [DATA_NEEDED: endurance cycles] | — |
| Data Retention | [DATA_NEEDED: data retention years] | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (legacy PQFP, lead-bearing) |
| Lead-Free | [DATA_NEEDED: lead-free] | — |
| Jenis Ingatan | — | Flash (NOR, Enhanced Configuration PROM) |
| Saiz Ingatan | — | 8 Mbit |
| Supply Voltage (Core) | — | 3.3 V |
| Supply Voltage (I/O) | — | 3.3 V |
| Antaramuka | — | Altera FPGA configuration serial/parallel (FPP) + JTAG (IEEE 1149.1) |
| In-System Programmability | — | IEEE Std. 1532 compliant |
| Programming Language | — | Jam STAPL |
| Boundary Scan | — | JTAG boundary-scan test supported |
| Data Compression | — | Yes (increases effective capacity) |
| Configuration Controller | — | On-chip, dedicated to Altera FPGAs |
| Initiate-Configuration Pin | — | nINIT_CONF (private JTAG instruction) |
| Jenis Pemasangan | — | Surface Mount |
| Compatible FPGAs | — | Stratix, Stratix II, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, Cyclone, Cyclone II, Arria GX, Stratix GX, Stratix II GX |