EPC8Q1100 vs EPC8QI100 比較

詳細並排比較 EPC8Q1100 由 Altera 與 EPC8QI100 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC8Q1100 EPC8QI100
品牌 Altera Intel
類別 FPGA & CPLD Memory ICs
生命週期狀態 最後購買 Obsolete
Product Type Enhanced Configuration Device (boot PROM) —
Memory Density 8 Mbit (8,388,608 bits) —
Supported FPGAs Altera SRAM-based LUT FPGAs (Cyclone, Stratix, APEX, ACEX, Mercury, Excalibur) —
Configuration Interface Altera Enhanced Config serial interface (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) —
Max DCLK Frequency 33 MHz (Fast-mode) —
Supply Voltage (VCC) 3.0 V to 3.6 V —
Supply Voltage (VCCIO for FPGA interface) 1.8 V / 2.5 V / 3.3 V tolerant —
Programming Interface IEEE Std 1149.1 JTAG (ISP) + serial byte-blaster mode —
In-System Programmable Yes —
封裝 100-pin PQFP (plastic quad flat pack) 100-PQFP (20 x 14 mm)
工作溫度 -40 C to +85 C (industrial) -40C to +85C (industrial)
Operating Current (active read) [DATA_NEEDED: active ICC] —
Standby Current [DATA_NEEDED: ICC standby] —
Endurance (program/erase cycles) [DATA_NEEDED: endurance cycles] —
Data Retention [DATA_NEEDED: data retention years] —
RoHS 狀態 [DATA_NEEDED: RoHS status] Non-compliant (legacy PQFP, lead-bearing)
Lead-Free [DATA_NEEDED: lead-free] —
記憶體類型 — Flash (NOR, Enhanced Configuration PROM)
記憶體容量 — 8 Mbit
Supply Voltage (Core) — 3.3 V
Supply Voltage (I/O) — 3.3 V
介面 — Altera FPGA configuration serial/parallel (FPP) + JTAG (IEEE 1149.1)
In-System Programmability — IEEE Std. 1532 compliant
Programming Language — Jam STAPL
Boundary Scan — JTAG boundary-scan test supported
Data Compression — Yes (increases effective capacity)
Configuration Controller — On-chip, dedicated to Altera FPGAs
Initiate-Configuration Pin — nINIT_CONF (private JTAG instruction)
安裝類型 — Surface Mount
Compatible FPGAs — Stratix, Stratix II, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, Cyclone, Cyclone II, Arria GX, Stratix GX, Stratix II GX

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