EPM5032DC-2 vs EPM5032DC20 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5032DC-2 disebabkan oleh Altera dan EPM5032DC20 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM5032DC-2 EPM5032DC20
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Product Type CPLD (Complex Programmable Logic Device) UV-erasable PLD (CPLD class)
Series MAX 5000 —
Macrocells 32 32
Usable Gates (typical) 600 —
Logic Array Blocks (LABs) 4 —
Kemasan 20-pin CDIP (Ceramic DIP) 20-pin Ceramic DIP (DC) with UV window
Speed Grade -2 (tPD ~25 ns, commercial) —
Configuration Memory EPROM (one-time programmable per generation; UV-erasable variants exist) —
Supply Voltage (VCC) 5 V (single supply, +/-5%) 5 V (4.75 V to 5.25 V)
Suhu Operasi 0C to +70C (commercial grade) [DATA_NEEDED: operating temperature range]
Programmable Pins / I/O 20 pins (JEDEC-standard 0.300" ceramic DIP) —
Programming Interface Altera ByteBlaster / parallel-port JTAG-style ISP —
Interconnect Programmable Interconnect Array (PIA) with deterministic timing —
Status RoHS [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] [DATA_NEEDED: RoHS compliance]
Jenis Pemasangan Through-Hole (DIP) Through-Hole (DIP)
Aras MSL Not applicable (through-hole hermetic ceramic) —
Device Family — MAX 5000
Usable Gates — 600
Propagation Delay (tPD) — 20 ns
Maximum Frequency (Fmax) — 71.4 MHz
Dedicated Inputs — 7
I/O Pins — 16 (bidirectional)
Total Inputs (max) — 24
Output Macrocells — 16
Clock Inputs — 1 (global)
Architecture — PAL-type with Programmable Interconnect Array (PIA)
Process Technology — CMOS

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