EPM5032DC-2 vs EPM5032DC20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032DC-2 sa pamamagitan ng Altera at EPM5032DC20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5032DC-2 EPM5032DC20
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Type CPLD (Complex Programmable Logic Device) UV-erasable PLD (CPLD class)
Series MAX 5000 —
Macrocells 32 32
Usable Gates (typical) 600 —
Logic Array Blocks (LABs) 4 —
Packhaging 20-pin CDIP (Ceramic DIP) 20-pin Ceramic DIP (DC) with UV window
Speed Grade -2 (tPD ~25 ns, commercial) —
Configuration Memory EPROM (one-time programmable per generation; UV-erasable variants exist) —
Supply Voltage (VCC) 5 V (single supply, +/-5%) 5 V (4.75 V to 5.25 V)
Temperature na Operasyon 0C to +70C (commercial grade) [DATA_NEEDED: operating temperature range]
Programmable Pins / I/O 20 pins (JEDEC-standard 0.300" ceramic DIP) —
Programming Interface Altera ByteBlaster / parallel-port JTAG-style ISP —
Interconnect Programmable Interconnect Array (PIA) with deterministic timing —
Tindminan RoHS [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] [DATA_NEEDED: RoHS compliance]
Uri ng Pagpapasok Through-Hole (DIP) Through-Hole (DIP)
Level ng MSL Not applicable (through-hole hermetic ceramic) —
Device Family — MAX 5000
Usable Gates — 600
Propagation Delay (tPD) — 20 ns
Maximum Frequency (Fmax) — 71.4 MHz
Dedicated Inputs — 7
I/O Pins — 16 (bidirectional)
Total Inputs (max) — 24
Output Macrocells — 16
Clock Inputs — 1 (global)
Architecture — PAL-type with Programmable Interconnect Array (PIA)
Process Technology — CMOS

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