EPM5192ALI84-20 vs EPM5192ALC84-15 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5192ALI84-20 disebabkan oleh Altera dan EPM5192ALC84-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM5192ALI84-20 - 192-Macrocell MAX 5000 PLD, 84-Pin J-Lead | Altera
EPM5192ALI84-20 ObsoletePengandingan Spesifikasi
| Parametr | EPM5192ALI84-20 | EPM5192ALC84-15 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (UV-erasable / OTP Complex PLD) | CPLD / UV-Erasable / OTP Complex PLD |
| Macrocells | 192 | 192 |
| Process Technology | CMOS, EPROM-based | CMOS (EPROM-based) |
| Propagation Delay (tPD) | 20 ns (pin-compatible speed grade) | 15 ns |
| User I/O Pins (max) | 84 (in PLCC-84 package) | — |
| Tegangan Pemberi Arus | 5 V (single supply, TTL-compatible I/O) | — |
| Operating Temperature Grade | Industrial (I) | Commercial |
| Package Code | QCCJ (Plastic Leaded Chip Carrier, J-bend) | QCCJ |
| Package Type | PLCC-84 (PQCC-84) | — |
| No. of Terminals | 84 | — |
| Form of Terminal | J-BEND | — |
| Jenis Pemasangan | Surface Mount (PLCC socket compatible) | — |
| Programmability | UV-erasable / one-time programmable (OTP) | UV-erasable window / OTP |
| Logic Type | Combinatorial and registered, per-macrocell DFF | — |
| I/O Standard | TTL-compatible | — |
| Status RoHS | [DATA_NEEDED: RoHS status - Altera MAX 5000 series is generally legacy and may not be RoHS compliant] | — |
| Device Family | — | MAX 5000 (EPM5192) |
| Dedicated Inputs | — | 7 |
| User I/O Pins | — | 64 |
| Propagation Delay (Industry Variant) | — | 25 ns (per MicrochipUSA listing) |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (nominal 5 V) |
| Kemasan | — | 84-pin PLCC (QCCJ, J-bend ceramic) |
| Terminal Form | — | J-BEND |
| Package Shape | — | SQUARE |
| Architecture | — | Programmable Logic Array + Macrocell Registers + PIA interconnect |