EPM5192JC-1 vs EPM5192JC-ES Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5192JC-1 disebabkan oleh Altera dan EPM5192JC-ES disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM5192JC-1 EPM5192JC-ES
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 5000 —
Device Type CPLD - Complex Programmable Logic Device CPLD (EPLD)
Technology CMOS, UV-Erasable / OTP CMOS
Macrocells 192 192
Usable Gates 3750 —
Propagation Delay (tPD) 40 ns (speed grade -1) —
Maximum Internal Frequency (fMAX) 62.5 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V —
User I/O Pins 84 [DATA_NEEDED: user I/O count for JC-ES in PLCC-84]
Package Type 84-pin Ceramic Quad Flat Pack (CQFP), windowed —
JEDEC Package Code S-CQCC-J84 —
Suhu Operasi 0 C to +70 C (commercial) [DATA_NEEDED: operating temperature range for ES grade]
Configuration Memory UV-EPROM (erasable under UV lamp) EPROM (UV-erasable, one-time programmable for JC-ES)
Programming Interface Altera MAX programming interface (parallel, pre-JTAG for this family) —
Process CMOS EPROM —
I/O Standard TTL/CMOS 5 V compatible —
Device Family — MAX 5000
Logic Array Blocks (LABs) — 12
Interconnect — Programmable Interconnect Array (PIA)
Kemasan — 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84)
Jenis Pemasangan — Surface Mount
Programming — Altera MAX+PLUS II or compatible programmer
Tegangan Pemberi Arus — [DATA_NEEDED: VCC nominal]
Status RoHS — [DATA_NEEDED: RoHS compliance]
Lead-Free — [DATA_NEEDED: lead-free status]
Aras MSL — [DATA_NEEDED: MSL rating]
Note — Datasheet source: Altera MAX 5000 family document, 52 pages

Laporan Datasheet & Sumber

Lihat Semua Produk Buat BOQ Minta Bao Harga