EPM5192JC-1 vs EPM5192JC-ES Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC-1 sa pamamagitan ng Altera at EPM5192JC-ES sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192JC-1 EPM5192JC-ES
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 —
Device Type CPLD - Complex Programmable Logic Device CPLD (EPLD)
Technology CMOS, UV-Erasable / OTP CMOS
Macrocells 192 192
Usable Gates 3750 —
Propagation Delay (tPD) 40 ns (speed grade -1) —
Maximum Internal Frequency (fMAX) 62.5 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V —
User I/O Pins 84 [DATA_NEEDED: user I/O count for JC-ES in PLCC-84]
Package Type 84-pin Ceramic Quad Flat Pack (CQFP), windowed —
JEDEC Package Code S-CQCC-J84 —
Temperature na Operasyon 0 C to +70 C (commercial) [DATA_NEEDED: operating temperature range for ES grade]
Configuration Memory UV-EPROM (erasable under UV lamp) EPROM (UV-erasable, one-time programmable for JC-ES)
Programming Interface Altera MAX programming interface (parallel, pre-JTAG for this family) —
Process CMOS EPROM —
I/O Standard TTL/CMOS 5 V compatible —
Device Family — MAX 5000
Logic Array Blocks (LABs) — 12
Interconnect — Programmable Interconnect Array (PIA)
Packhaging — 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84)
Uri ng Pagpapasok — Surface Mount
Programming — Altera MAX+PLUS II or compatible programmer
Volte ng Pagbibigay — [DATA_NEEDED: VCC nominal]
Tindminan RoHS — [DATA_NEEDED: RoHS compliance]
Lead-Free — [DATA_NEEDED: lead-free status]
Level ng MSL — [DATA_NEEDED: MSL rating]
Note — Datasheet source: Altera MAX 5000 family document, 52 pages

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