EPM7128STC100-15N vs EPM7128STC100-6N Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM7128STC100-15N disebabkan oleh Intel dan EPM7128STC100-6N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM7128STC100-15N EPM7128STC100-6N
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX 7000S MAX 7000S
Usable Gates 2,500 2,500
Macro Cells 128 128
Logic Array Blocks (LABs) 8 (16 macro cells each) —
Maximum User I/O 84 —
Pin-to-Pin Logic Delay (tPD) 15 ns (-15 speed grade) —
Maximum Internal Frequency 76.9 MHz 147.1 MHz
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) —
Supply Voltage (VCCIO) 3.3 V or 5 V (per bank) 5 V
Technology CMOS EEPROM, in-system programmable —
Kemasan 100-pin TQFP —
Suhu Operasi 0C to +70C (commercial) 0C to +70C (Commercial)
JTAG (IEEE 1149.1) Yes - in-system programming —
Output Options Totem-pole or open-drain (per pin) —
Dedicated Inputs 4 global inputs —
Status RoHS Non-RoHS (legacy SnPb finish typical) Non-Compliant (lead-bearing package)
Status Lingkungan Hidup Obsolete (PDN effective 2017-06-01) —
User I/Os — 84
Logic Family — CMOS
Bilangan Pin — 100
Package Type — TQFP-100
Internal Counter Frequency — 250 MHz
Propagation Delay (tPD) — 6 ns
Pin-to-Pin Delay — 4.5 ns
Process Technology — CMOS EEPROM
Programmability — In-System Programmable (ISP) via JTAG
JTAG Support — IEEE 1149.1 Boundary Scan
Jenis Pemasangan — Surface Mount

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