EPM7256SQC208-7N vs EPM7256SQC208-15N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM7256SQC208-7N disebabkan oleh Altera dan EPM7256SQC208-15N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM7256SQC208-7N | EPM7256SQC208-15N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 7000S | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | — |
| Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 164 | 164 |
| Speed Grade | -7 (7.5 ns pin-to-pin) | -15 |
| Maximum Frequency | 128.2 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS EEPROM | — |
| Configuration Memory | Non-volatile EEPROM (no external config needed) | EEPROM (non-volatile) |
| Kemasan | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin PQFP |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Suhu Operasi | Commercial (0C to +70C) | [DATA_NEEDED: operating temperature range] |
| JTAG Interface | IEEE 1149.1 boundary-scan (ISP capable) | IEEE 1149.1 boundary-scan |
| Minimum DC Input Voltage | -0.5 V | — |
| Input Undershoot Tolerance | -2.0 V for <100 mA, <20 ns | — |
| Status RoHS | Compliant (N suffix = lead-free) | Lead free / RoHS Compliant |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Open-Drain Output | Optional per I/O pin | — |
| Series | — | MAX 7000S |
| Pin-to-Pin Delay | — | 15 ns (speed grade -15) |
| Tegangan Pemberi Arus | — | 5 V |
| In-System Programmability | — | Yes (ISP) |
| Logic Array Blocks | — | 16 macrocells per LAB |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Product Category | — | CPLD - Complex Programmable Logic Devices |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |