EPM7512BQC208-5 vs EPM7512BQC208-10 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM7512BQC208-5 disebabkan oleh Altera dan EPM7512BQC208-10 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM7512BQC208-5 EPM7512BQC208-10
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete NRND
Family MAX 7000B MAX 7000B
Device Type EEPROM-based Complex Programmable Logic Device (CPLD) —
Macrocells 512 512
Usable Gates 10,000 10,000
User I/O Pins 176 —
Logic Array Blocks 16 —
Propagation Delay (tPD) 5 ns —
Internal Frequency 163.9 MHz —
Supply Voltage (VCCINT) 2.375 V to 2.625 V (2.5 V nominal) —
Programmable Type In System Programmable (ISP) In-System Programmable (EEPROM)
Configuration Memory EEPROM (non-volatile) —
Kemasan 208-pin PQFP (28x28 mm) —
Package Code FQFP / S-PQFP-G208 —
Terminal Pitch 0.5 mm —
Jenis Pemasangan Surface Mount Surface Mount
Suhu Operasi 0C to 70C (commercial) 0 C to +70 C (commercial)
JTAG Support IEEE 1149.1 boundary-scan —
Speed Grade -5 (fastest MAX 7000B grade) —
Status RoHS [DATA_NEEDED: RoHS status] unknown
Series — MAX 7000B
Logic Elements / Blocks — 32 LABs (16 macrocells per LAB)
User I/Os — 176
Propagation Delay (tpd) — 10 ns (max, pin-to-pin)
Internal Supply Voltage — 2.375 V to 2.625 V (nominal 2.5 V)
Kemasan / Case — 208-pin PQFP (28x28 mm), S-PQFP-G208
Architecture — CMOS, Multiple Array Matrix (MAX) second-generation
JTAG / Boundary Scan — IEEE Std 1149.1 compliant
Aras MSL — [DATA_NEEDED: MSL Level]

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