EPM9560RC-15 vs EPM9480RC240-15 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9560RC-15 disebabkan oleh Altera dan EPM9480RC240-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EPM9560RC-15 EPM9560RC-15 - 560-Macrocell MAX 9000 CPLD, 15ns, 240-RQFP | Altera / Intel

EPM9560RC-15 - 560-Macrocell MAX 9000 CPLD, 15ns, 240-RQFP | Altera / Intel

EPM9560RC-15 ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EPM9560RC-15 EPM9480RC240-15
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Masa Terakhir Dibeli Obsolete
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 560 —
Usable Gates 12,000 12,000
Logic Array Blocks (LABs) 16 (40 macrocells each) —
Maximum User I/O Pins 191 —
Pin-to-Pin Delay (tPD1) 15 ns —
Supply Voltage (VCCINT) 4.75 V to 5.25 V (5.0 V nominal) —
Suhu Operasi 0 C to +70 C (commercial) [DATA_NEEDED: operating temperature range]
Kemasan 240-pin RQFP (32x32 mm) 240-pin RQFP (32x32 mm)
Jenis Pemasangan Surface Mount Surface Mount
Programming Interface IEEE Std. 1149.1 JTAG (ISP) —
Process Technology CMOS EEPROM —
Architecture Multiple Array MatriX (MAX) - third generation —
Status RoHS [DATA_NEEDED: RoHS status] RoHS non-compliant
In-System Programmability Yes (5.0 V ISP via JTAG) —
Programmable Type — In System Programmable (ISP)
Device Family — MAX 9000
Macro Cells — 480
Pin-to-Pin Delay (tPD) — 15 ns
Internal Supply Voltage — 4.75 V to 5.25 V
Configuration Technology — EEPROM-based (non-volatile)
JTAG Interface — IEEE Std. 1149.1
Supplier Device Package — 240-RQFP (32x32)
Number of I/O Pins — [DATA_NEEDED: user I/O count]
Lead Free Status — [DATA_NEEDED: lead free status]
Logic Architecture — Multiple Array MatriX (MAX) third-generation
Supply Voltage (5.0 V nominal) — 5.0 V

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