EPM9560RI210-15 vs EPM9560RC208-15 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9560RI210-15 disebabkan oleh Altera dan EPM9560RC208-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM9560RI210-15 EPM9560RC208-15
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Family MAX 9000 (EPM9560) MAX 9000
Device Type Complex Programmable Logic Device (CPLD) EEPROM-based Complex Programmable Logic Device (CPLD)
Macrocells 560 —
Usable Gates 12,000 12,000 gates
Logic Array Blocks (LABs) 20 —
User I/O Pins 164 —
Pin-to-Pin Delay (tPD) 15 ns (-15 speed grade) —
Supply Voltage (VCCINT) 5.0 V —
I/O Voltage (MultiVolt) 3.3 V / 5.0 V compatible —
Configuration Memory EEPROM (non-volatile) —
In-System Programmability Yes (JTAG ISP) Yes, via IEEE Std. 1149.1 JTAG
JTAG Boundary Scan IEEE 1149.1 compliant —
Kemasan 210-pin RQFP (PowerQuad) 208-pin RQFP (Power Quad Flat Pack)
Suhu Operasi Industrial (-40C to +85C) [DATA_NEEDED: operating temperature range]
Jenis Pemasangan Surface Mount Surface Mount
Status RoHS ROHS3 Compliant [DATA_NEEDED: RoHS status]
Tingkat sensitiviti Air Nama (MSL) 3 (168 Hours) —
Manufacturer Standard Lead Time 1-7 Days (distributor stock) —
Macro Cells — 560 macro cells
Pin-to-Pin Delay — 15 ns
Counter Speed — 117.6 MHz
Tegangan Pemberi Arus — 5.0 V
Configuration Technology — EEPROM (non-volatile)
Number of I/O Pins — [DATA_NEEDED: number of I/O pins]
Logic Array Blocks — [DATA_NEEDED: number of logic array blocks]
Speed Grade — -15 (15 ns pin-to-pin)
Architecture — Third-generation Multiple Array MatriX (MAX)

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