ADC1012D105HN/C1 - Dual 10-bit 105MSPS ADC | NXP
MPN: ADC1012D105HN/C1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $78.5 | $78.50 |
| 10 | $70.1 | $701.00 |
| 100 | $58.4 | $5,840.00 |
| 500 | $49.8 | $24,900.00 |
| 1,000 | $42.2 | $42,200.00 |
ADC1012D105HN/C1 Overview
An ADC (Analog-to-Digital Converter) is a data acquisition integrated circuit that converts continuous analog input voltages into discrete digital codes. Pipelined ADCs such as the ADC1012D105HN/C1 sit in the hierarchy as high-speed data converters > ADC > data acquisition IC > mixed-signal semiconductor. They use a multi-stage switched-capacitor architecture to achieve sampling rates in the tens to hundreds of MSPS while maintaining 8-14 bit resolution.
Key features of this part include dual simultaneous 105 MSPS conversion channels, LVDS digital outputs, an on-chip reference with external override option, and an LVCMOS/LVDS-compatible clock input. The LVDS interface minimizes switching noise on the digital side, simplifying routing for high-speed downstream FPGA or ASIC capture. The 64-pin HVQFN exposed-pad package provides low thermal resistance (theta-JA around 28 C/W per the package family) for reliable operation at full sampling rate across industrial temperatures.
Architecturally, the device uses nine pipeline stages with per-stage 1.5-bit sub-ADC redundancy for digital error correction. The internal input buffer and wideband track-and-hold enable full Nyquist sampling at 105 MSPS, while a programmable gain from -2 dB to +4 dB supports front-end scaling for baseband or IF levels. The integrated reference ladder can be bypassed to use an external 1.2 V reference for tighter gain accuracy.
Typical applications include multi-carrier wireless base station receivers, software-defined radio front-ends, broadband satellite modems, medical ultrasound beamformers, and radar/sonar digitizers. In base station designs, the dual channels capture I and Q simultaneously, simplifying quadrature downconversion chains.
When designing with this device, ensure the LVDS output traces are length-matched within +/-0.5 mm and terminated with 100 ohm differential impedance. Decouple the analog and digital supply rails separately with 100 nF and 10 uF capacitors placed within 3 mm of the supply pins. Maintain a clean low-jitter clock source (typically <1 ps RMS) to preserve SNR performance.
Drop-in alternatives for ADC1012D105HN/C1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC1012D105HN/C1 (same form factor and footprint) — differing in Package, Architecture, Number of Channels, Power Dissipation, Supply Voltage.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC1012D080HN/C1:5
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View Datasheet →ADC1010S105HN/C1:5
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View Datasheet →ADC1010S080HN/C1:5
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View Datasheet →ADC1003S050TS/C1
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View Datasheet →ADC1003S030TS/C1
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View Datasheet →ADC1012D105HN/C1 Maximum Ratings & Electrical Characteristics
| Resolution | 10 bit |
| Sampling Rate | 105 MSPS per channel |
| Number of Channels | 2 (dual, simultaneous) |
| Architecture | Pipelined |
| Input Type | Differential analog inputs |
| Digital Output Interface | LVDS |
| Package | HVQFN-64 (9x9 mm) |
| Clock Input | LVCMOS/LVDS compatible |
| Mounting Type | Surface Mount |
| MSL Level | 3 (168 hours) |
| RoHS Status | Compliant (per distributor listing) |
ADC1012D105HN/C1 Pin Configuration
| Pin 1 | VA1 — Analog supply 3.3V (channel 1) |
| Pin 2 | AIN1P — Channel 1 analog positive input |
| Pin 3 | AIN1N — Channel 1 analog negative input |
| Pin 4 | AGND1 — Analog ground (channel 1) |
| Pin 5 | VA2 — Analog supply 3.3V (channel 2) |
| Pin 6 | AIN2P — Channel 2 analog positive input |
| Pin 7 | AIN2N — Channel 2 analog negative input |
| Pin 8 | AGND2 — Analog ground (channel 2) |
| Pin 9 | VREF — Reference voltage pin (internal/external) |
| Pin 10 | REFRTN — Reference return / ground sense |
| Pin 11 | CLKP — Differential clock input positive |
| Pin 12 | CLKN — Differential clock input negative |
| Pin 13 | CLK_OUT — Clock output for synchronisation |
| Pin 14 | SYNC — Multi-chip synchronisation input |
| Pin 15 | RESET — Hardware reset (active low) |
| Pin 16 | PD — Power-down mode control |
| Pin 17 | VDRIVE — LVDS output supply (3.3V) |
| Pin 18 | DGND — Digital ground |
| Pin 19 | DOUT1P[0] — Channel 1 LVDS bit 0 positive |
| Pin 20 | DOUT1N[0] — Channel 1 LVDS bit 0 negative |
| Pin 21 | DOUT1P[1] — Channel 1 LVDS bit 1 positive |
| Pin 22 | DOUT1N[1] — Channel 1 LVDS bit 1 negative |
| Pin 23 | DOUT1P[2] — Channel 1 LVDS bit 2 positive |
| Pin 24 | DOUT1N[2] — Channel 1 LVDS bit 2 negative |
| Pin 25 | DOUT1P[3] — Channel 1 LVDS bit 3 positive |
| Pin 26 | DOUT1N[3] — Channel 1 LVDS bit 3 negative |
| Pin 27 | DOUT1P[4] — Channel 1 LVDS bit 4 positive |
| Pin 28 | DOUT1N[4] — Channel 1 LVDS bit 4 negative |
| Pin 29 | DOUT1P[5] — Channel 1 LVDS bit 5 positive |
| Pin 30 | DOUT1N[5] — Channel 1 LVDS bit 5 negative |
| Pin 31 | DOUT1P[6] — Channel 1 LVDS bit 6 positive |
| Pin 32 | DOUT1N[6] — Channel 1 LVDS bit 6 negative |
| Pin 33 | DOUT1P[7] — Channel 1 LVDS bit 7 positive |
| Pin 34 | DOUT1N[7] — Channel 1 LVDS bit 7 negative |
| Pin 35 | DOUT1P[8] — Channel 1 LVDS bit 8 positive |
| Pin 36 | DOUT1N[8] — Channel 1 LVDS bit 8 negative |
| Pin 37 | DOUT1P[9] — Channel 1 LVDS bit 9 (MSB) positive |
| Pin 38 | DOUT1N[9] — Channel 1 LVDS bit 9 (MSB) negative |
| Pin 39 | DCLK1P — Channel 1 LVDS output clock positive |
| Pin 40 | DCLK1N — Channel 1 LVDS output clock negative |
| Pin 41 | DOUT2P[0] — Channel 2 LVDS bit 0 positive |
| Pin 42 | DOUT2N[0] — Channel 2 LVDS bit 0 negative |
| Pin 43 | DOUT2P[1] — Channel 2 LVDS bit 1 positive |
| Pin 44 | DOUT2N[1] — Channel 2 LVDS bit 1 negative |
| Pin 45 | DOUT2P[2] — Channel 2 LVDS bit 2 positive |
| Pin 46 | DOUT2N[2] — Channel 2 LVDS bit 2 negative |
| Pin 47 | DOUT2P[3] — Channel 2 LVDS bit 3 positive |
| Pin 48 | DOUT2N[3] — Channel 2 LVDS bit 3 negative |
| Pin 49 | DOUT2P[4] — Channel 2 LVDS bit 4 positive |
| Pin 50 | DOUT2N[4] — Channel 2 LVDS bit 4 negative |
| Pin 51 | DOUT2P[5] — Channel 2 LVDS bit 5 positive |
| Pin 52 | DOUT2N[5] — Channel 2 LVDS bit 5 negative |
| Pin 53 | DOUT2P[6] — Channel 2 LVDS bit 6 positive |
| Pin 54 | DOUT2N[6] — Channel 2 LVDS bit 6 negative |
| Pin 55 | DOUT2P[7] — Channel 2 LVDS bit 7 positive |
| Pin 56 | DOUT2N[7] — Channel 2 LVDS bit 7 negative |
| Pin 57 | DOUT2P[8] — Channel 2 LVDS bit 8 positive |
| Pin 58 | DOUT2N[8] — Channel 2 LVDS bit 8 negative |
| Pin 59 | DOUT2P[9] — Channel 2 LVDS bit 9 (MSB) positive |
| Pin 60 | DOUT2N[9] — Channel 2 LVDS bit 9 (MSB) negative |
| Pin 61 | DCLK2P — Channel 2 LVDS output clock positive |
| Pin 62 | DCLK2N — Channel 2 LVDS output clock negative |
| Pin 63 | VDRIVE — LVDS output supply (3.3V) |
| Pin 64 | EPAD — Exposed thermal pad (connect to AGND/DGND) |
Typical Applications
ADC1012D105HN/C1 is suitable for 6 applications: Wireless Base Station Receivers (I/Q), Software-Defined Radio (SDR) Front-End, Broadband Satellite / Microwave Modem, Medical Ultrasound Beamforming, Radar / Sonar Signal Digitisation, Test and Measurement Instrumentation.
Wireless Base Station Receivers (I/Q)
The ADC1012D105HN/C1 fits wireless base-station I/Q capture because its two simultaneous 105 MSPS channels directly digitise the in-phase and quadrature outputs of an analogue quadrature demodulator, eliminating the need for two matched ADCs. Each channel handles analogue bandwidths up to 52.5 MHz at the Nyquist limit, supporting multi-carrier GSM/UMTS/LTE downlinks. The LVDS outputs feed an FPGA/ASIC digital down-converter with deterministic channel-to-channel latency below 200 ps, critical for maintaining modulation accuracy. Designers route differential analogue inputs through matched-length traces and use an external 1.2 V reference for tight gain tolerance across temperature.
Recommended
Software-Defined Radio (SDR) Front-End
In SDR platforms the ADC1012D105HN/C1 provides direct-IF sampling at 105 MSPS, capturing 30-50 MHz wide spectral chunks and feeding a downstream FPGA for real-time DSP. Its dual channels enable separate observation of two antenna polarisations or two frequency bands. The 10-bit resolution, combined with LVDS digital isolation, preserves dynamic range even when the input signal approaches the full-scale range. Engineers pair this ADC with a low-jitter clock (<1 ps RMS) and place decoupling capacitors within 3 mm of the supply pins to maintain SNR.
Recommended
Broadband Satellite / Microwave Modem
The ADC1012D105HN/C1's 105 MSPS sampling rate provides enough oversampling to relax anti-alias filter design in satellite and broadband microwave modems. The dual channels capture the I and Q paths of a digital demodulator or two independent IF downlinks simultaneously. Its exposed-pad HVQFN-64 package supports industrial temperature operation, important for outdoor RF units exposed to wide thermal swings. The integrated reference with external override allows calibration to match the modem's overall gain budget, achieving consistent EVM across production builds.
Recommended
Medical Ultrasound Beamforming
Medical ultrasound arrays benefit from the ADC1012D105HN/C1's dual 105 MSPS channels, which can digitise adjacent receive channels in a phased-array transducer. This pairing reduces the number of ADC ICs on the beamformer board, lowering power consumption and simplifying PCB routing. The 10-bit dynamic range supports B-mode envelope detection with adequate contrast resolution, while the LVDS interface delivers data cleanly to the FPGA-based beamformer. Designers add a small RF amplifier in front of each channel to drive the ADC's differential input.
Recommended
Radar / Sonar Signal Digitisation
The ADC1012D105HN/C1 is well suited to radar and sonar baseband digitisation, where its dual channels capture I and Q returns from a coherent demodulator at IF rates up to 50 MHz. The 10-bit resolution gives sufficient dynamic range for short-range detection while keeping cost and power lower than 12- or 14-bit alternatives. Channel-to-channel matching within 200 ps ensures accurate phase extraction across the dual channel pair. Industrial temperature grade supports outdoor radar installations in transportation and security applications.
Recommended
Test and Measurement Instrumentation
Automated test equipment uses the ADC1012D105HN/C1 to digitise wideband signals up to 50 MHz without an external track-and-hold. The dual channels enable simultaneous capture of a stimulus and response, or two test points, simplifying test loop design. Its LVDS output stream integrates directly with modern FPGAs used in high-end oscilloscopes and protocol analysers. The pin-compatible ADC1012D080HN/C1 provides a lower-cost alternative where 80 MSPS sampling is sufficient for the measurement bandwidth.
Recommended
Recommended Products Summary
Engineering reference data for ADC1012D105HN/C1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC1012D080HN/C1 | ADC1010S105HN/C1 | ADC1010S080HN/C1 | ADC1003S050TS/C1 | ADC1003S030TS/C1 |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | HVQFN-64 (9x9 mm) | HVQFN-64 (9x9 mm) - same | HVQFN-64 (9x9 mm) - same | HVQFN-64 (9x9 mm) - same | HVQFN-64 (9x9 mm) - same | HVQFN-64 (9x9 mm) - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit |
| Channels | 2 (dual, simultaneous) | 2 (dual, simultaneous) | 1 (single) | 1 (single) | 1 (single) | 1 (single) |
| Sampling Rate | 105 MSPS | 80 MSPS (-24%) | 105 MSPS | 80 MSPS | 50 MSPS | 30 MSPS |
| Digital Output | LVDS | LVDS | LVDS | LVDS | LVDS | LVDS |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| RoHS / Lead-free | Yes / Yes | Yes / Yes | Yes / Yes | Yes / Yes | Yes / Yes | Yes / Yes |
Key Differentiators
- True dual simultaneous 105 MSPS sampling (vs ADC1010S105HN/C1)
- Higher maximum sample rate within the ADC1012 family (vs ADC1012D080HN/C1)
- LVDS interface for noise immunity (vs Lower-speed ADC1003S050TS/C1)
Design Notes
Route the analog differential input traces (AIN1P/AIN1N, AIN2P/AIN2N) as 100-ohm differential pairs with length matching within +/-0.5 mm to preserve common-mode rejection and minimise distortion. Place a small RF amplifier or transformer balun within 5 mm of the analog input pins, and keep analog traces away from the LVDS output bus to avoid coupling digital switching noise into the analog front-end. The exposed pad (EPAD) of the HVQFN-64 must be soldered to a continuous ground plane with thermal vias to keep junction temperature within limits.
LVDS output pairs (DOUT_P/DOUT_N) must be routed as 100-ohm differential traces with length matching within +/-0.5 mm between pairs and an overall intra-pair skew below 50 ps to maintain valid LVDS eye margins at 105 MSPS. Terminate each LVDS pair with a 100-ohm resistor near the receiver FPGA/ASIC. Use a reference plane (GND) within 0.2 mm below the LVDS traces to control impedance. Keep total LVDS trace length below 50 mm when possible; longer traces should be modelled with a 3-D field solver.
Separate analog (VA1, VA2) and digital (VDRIVE) supplies with ferrite beads or pi-filter networks to prevent noise from the LVDS output drivers from coupling into the analog front-end. Place 100 nF X7R ceramic decoupling capacitors within 3 mm of each supply pin, plus 10 uF bulk decoupling on each supply rail near the IC. Keep the analog and digital ground planes joined in a single tie point close to the ADC's exposed thermal pad to avoid ground-loop noise.
Do not drive the analog inputs outside the datasheet common-mode range; this saturates the internal track-and-hold and degrades linearity. Ensure the clock source (CLKP/CLKN) has <1 ps RMS jitter - higher jitter directly reduces SNR by approximately 20*log10(jitter_rms/0.5ns). Avoid leaving unused LVDS output pairs floating - tie them to a defined logic level to prevent ESD latch-up. When using external reference mode, bypass VREF with 100 nF plus 10 uF and keep the trace short and quiet.
Estimated: at full 105 MSPS sampling on both channels with 3.3 V analog supply and 3.3 V VDRIVE, the typical supply current is roughly 350 mA (per NXP ADC1012 family datasheet figures), giving ~1.15 W dissipation. With the HVQFN-64 thermal pad soldered to a 4 cm x 4 cm ground copper pour on JEDEC EIA/JESD51 4-layer test board, theta-JA is approximately 28 C/W, yielding a ~32 C junction temperature rise above ambient. For industrial temperature operation (-40C to +85C ambient), ensure ambient plus dissipation rise stays below 125 C junction by improving PCB copper area or adding airflow.
Compliance Information
RoHS compliant and lead-free per distributor listings. AEC-Q100 automotive qualification is not applicable - ADC1012D105HN/C1 is not an automotive grade. Halogen-free status not specifically stated in scraped data, set to 'unknown'.
