ADC34J24IRGZ25 - Quad 12-Bit 125 MSPS JESD204B ADC | Texas Instruments
MPN: ADC34J24IRGZ25 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $42.5 | $42.50 |
| 10 | $38.2 | $382.00 |
| 100 | $33.8 | $3,380.00 |
| 500 | $30.1 | $15,050.00 |
| 1,000 | $26.75 | $26,750.00 |
ADC34J24IRGZ25 Overview
What is a JESD204B ADC? JESD204B is a high-speed serial interface standard (JEDEC JESD204B, revision 2011) that converts parallel LVDS data into a small number of differential serial lanes. It eliminates the wide parallel bus of older ADCs, reducing PCB area, lane count, and skew problems in multi-channel systems. An ADC in the ADC34Jxx family is a pipelined successive-approximation hybrid converter (pipelined core) with internal dither, designed for direct sampling of IF/RF signals in 4G/5G base stations, radar, and industrial imaging where multi-channel synchronization is required.
The device integrates a flexible input clock buffer with divide-by-1, -2, and -4 options, allowing one of three JESD204B lane rates to be selected from a common reference oscillator. Internal dither improves SFDR for small-swing inputs near full scale. According to the TI product page for ADC34J24, this part is pin-to-pin compatible with the 14-bit ADC34J25 family, enabling a single PCB to support either resolution tier.
Typical applications include wireless base-station receivers (4G LTE, 5G NR, multi-carrier GSM), phased-array radar digitizers, medical ultrasound beamformers, industrial digitizers, and multi-channel test & measurement. The industrial temperature grade (-40C to +85C) and 48-VQFN exposed-pad package support compact, fan-less embedded designs.
When designing with this ADC, use a low-noise LDO (e.g., a TPS7A47xx family part) to derive the AVDD_1V8 rail from a system supply, and keep the analog input traces length-matched to preserve 105 dB channel-to-channel isolation. The exposed thermal pad (EP) must be soldered to a continuous ground plane on the top layer for proper heat dissipation, since the device dissipates roughly 800 mW total at 125 MSPS across four channels.
Drop-in alternatives for ADC34J24IRGZ25 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC34J24IRGZ25 (same form factor and footprint) — differing in Package, Number of Channels, Reference Type, Resolution, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC34J25IRGZ25
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$24.1 / Unit
View Datasheet →ADC34J24IRGZT
✅ Drop-In📋 Reference alternative (not in catalog)
ADC34J24IRGZR
✅ Drop-In📋 Reference alternative (not in catalog)
ADC34J25IRGZT
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ADC34J24IRGZ25G4
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ADC3242IRGZ25
✅ Drop-In✓ In Stock
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View Datasheet →ADC34J24IRGZ25 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bit |
| Number of Channels | 4 |
| Sampling Rate (per channel) | 125 MSPS |
| Sampling Rate Range (family) | 50 MSPS to 160 MSPS |
| Input Type | Differential |
| Data Interface | JESD204B |
| Architecture | Pipelined |
| Reference Type | External |
| SNR (fIN = 70 MHz, -1 dBFS) | 69.6 dBFS |
| SFDR (fIN = 70 MHz, -1 dBFS) | 86 dBc |
| Channel Isolation | 105 dB |
| Supply Voltage | 1.8 V |
| Power Consumption (per channel, 160 MSPS) | 203 mW |
| Operating Temperature | -40C to +85C |
| Package | 48-VQFN (RGZ) 7x7 mm |
| Input Clock Divider | Divide-by-1, -2, -4 |
| Internal Dither | Yes |
| RoHS Status | Compliant |
ADC34J24IRGZ25 Pin Configuration
| Pin 1 | AINP0 — Differential analog input, channel 0 positive |
| Pin 2 | AINN0 — Differential analog input, channel 0 negative |
| Pin 3 | AVDD1V8_A — Analog 1.8 V supply, channel A |
| Pin 4 | AVSS_A — Analog ground, channel A |
| Pin 5 | AINP1 — Differential analog input, channel 1 positive |
| Pin 6 | AINN1 — Differential analog input, channel 1 negative |
| Pin 7 | AVDD1V8_B — Analog 1.8 V supply, channel B |
| Pin 8 | AVSS_B — Analog ground, channel B |
| Pin 9 | AINP2 — Differential analog input, channel 2 positive |
| Pin 10 | AINN2 — Differential analog input, channel 2 negative |
| Pin 11 | AVDD1V8_C — Analog 1.8 V supply, channel C |
| Pin 12 | AVSS_C — Analog ground, channel C |
| Pin 13 | AINP3 — Differential analog input, channel 3 positive |
| Pin 14 | AINN3 — Differential analog input, channel 3 negative |
| Pin 15 | AVDD1V8_D — Analog 1.8 V supply, channel D |
| Pin 16 | AVSS_D — Analog ground, channel D |
| Pin 17 | REF_CAP — Internal reference decoupling cap pin |
| Pin 18 | GND — Common ground reference |
| Pin 19 | CLK_INP — Sampling clock input, positive |
| Pin 20 | CLK_INN — Sampling clock input, negative |
| Pin 21 | VDD1V8_CLK — Clock 1.8 V supply |
| Pin 22 | VSS_CLK — Clock ground |
| Pin 23 | SYNC_N — JESD204B SYNC~ input |
| Pin 24 | SYSREF — JESD204B SYSREF input |
| Pin 25 | VDD1V8_DC — Digital core 1.8 V supply |
| Pin 26 | VSS_DC — Digital core ground |
| Pin 27 | RESETN — Hardware reset, active low |
| Pin 28 | SCLK — Serial configuration clock |
| Pin 29 | SDATA — Serial configuration data |
| Pin 30 | CS_N — Chip select, active low |
| Pin 31 | SDO — Serial configuration read-back |
| Pin 32 | VDD1V8_DRV — Output driver 1.8 V supply |
| Pin 33 | VSS_DRV — Output driver ground |
| Pin 34 | JESD0P — JESD204B serial lane 0 positive |
| Pin 35 | JESD0N — JESD204B serial lane 0 negative |
| Pin 36 | JESD1P — JESD204B serial lane 1 positive |
| Pin 37 | JESD1N — JESD204B serial lane 1 negative |
| Pin 38 | PDN — Power-down input |
| Pin 39 | GND — Common ground |
| Pin 40 | NC — Not connected (per datasheet) |
| Pin 41 | NC — Not connected (per datasheet) |
| Pin 42 | NC — Not connected (per datasheet) |
| Pin 43 | NC — Not connected (per datasheet) |
| Pin 44 | NC — Not connected (per datasheet) |
| Pin 45 | NC — Not connected (per datasheet) |
| Pin 46 | NC — Not connected (per datasheet) |
| Pin 47 | NC — Not connected (per datasheet) |
| Pin 48 | EP — Exposed thermal pad - solder to ground plane |
Typical Applications
ADC34J24IRGZ25 is suitable for 6 applications: 4G LTE / 5G NR Base-Station Receiver, Phased-Array Radar Digitizer, Medical Ultrasound Beamformer, Multi-Channel Test & Measurement, Software-Defined Radio (SDR) Capture, Industrial Vibration & Acoustic Monitoring.
4G LTE / 5G NR Base-Station Receiver
The ADC34J24IRGZ25's quad-channel differential inputs and 125 MSPS per channel make it a strong fit for 4G/5G base-station remote radio units (RRUs) that digitize four antenna streams. Per the TI product page, 69.6 dBFS SNR and 86 dBc SFDR at 70 MHz give sufficient dynamic range for multi-carrier LTE and NR; the JESD204B interface routes the four lanes to a Kintex/Artix FPGA over a single board-to-board connector. Each channel's 105 dB isolation prevents cross-talk between MIMO streams, and the 203 mW-per-channel figure keeps junction temperature manageable on a fan-less radio board. Design tip: place the ADC within 50 mm of the FPGA to keep JESD204B link margins healthy and use an LDO such as TPS7A4700 to derive the 1.8 V AVDD from a 5 V system rail.
Recommended
Phased-Array Radar Digitizer
In phased-array radar systems, the ADC34J24IRGZ25 digitizes four antenna sub-array channels at 125 MSPS, supporting L-band and S-band IF sampling where the 69.6 dBFS SNR at 70 MHz and 86 dBc SFDR preserve signal integrity for doppler and angle-of-arrival processing. Per the TI product page, internal dither reduces spurious content for sub-LSB input amplitudes, important when the radar return sits near the noise floor. The JESD204B interface synchronizes all four channels through SYSREF, achieving deterministic sub-sample latency for beam steering. The 48-VQFN exposed-pad package dissipates roughly 800 mW; a continuous ground plane top-layer pour (4 thermal vias under the EP) is required to keep the junction below 85 C at 125 C ambient.
Recommended
Medical Ultrasound Beamformer
The ADC34J24IRGZ25's four differential channels at 125 MSPS support mid-tier ultrasound beamformers that need to digitize transducer arrays at 30-40 MHz IF without external analog demodulation. Per the TI product page, the 105 dB channel-to-channel isolation prevents cross-element interference that would degrade beam-pattern side-lobe performance. The 1.8 V single-supply operation simplifies the power-tree of portable cart-based ultrasound units. The 12-bit resolution is sufficient for grayscale B-mode imaging; for harmonic imaging or 4D probes, the pin-compatible 14-bit ADC34J25IRGZ25 drop-in upgrade is recommended. Power consumption of 203 mW per channel at 160 MSPS supports fan-less cart designs where acoustic noise must be minimized.
Recommended
Multi-Channel Test & Measurement
For 4-channel oscilloscope front-ends and arbitrary-waveform analyzer capture cards, the ADC34J24IRGZ25 offers 12-bit 125 MSPS performance that competes with mid-range bench instruments. Per the TI product page, the 86 dBc SFDR at 70 MHz is adequate for spectrum-analyzer cards where intermodulation distortion is the limiting factor. The JESD204B interface allows multiple ADCs to be daisy-chained to a single Kintex-7 FPGA over 1-2 lanes per ADC, simplifying the digital backplane. The exposed-pad 48-VQFN package supports a 7x7 mm footprint, which fits compact modular-instrument cards. Designers should budget 800 mW total ADC dissipation and use a 4-layer FR4 stack-up with a continuous ground plane.
Recommended
Software-Defined Radio (SDR) Capture
Wideband software-defined radio platforms that digitize 0-100 MHz spectrum benefit from the ADC34J24IRGZ25's 125 MSPS per channel and 69.6 dBFS SNR at 70 MHz, per the TI product page. The four differential inputs let a single ADC handle two I/Q channels plus a reference and a monitoring channel on a single chip. The JESD204B interface keeps the FPGA-to-ADC bus as a 2-lane serial link, freeing FPGA I/O for DSP and network ports. The industrial -40C to +85C operating range supports outdoor or vehicle-mounted SDR deployments. The 1.8 V single-supply simplifies the power tree, and a low-noise LDO (TPS7A4700) is recommended to achieve datasheet noise performance.
Recommended
Industrial Vibration & Acoustic Monitoring
Vibration-monitoring systems on rotating machinery (motors, turbines, pumps) use the ADC34J24IRGZ25's four differential channels to sample IEPE accelerometers at 125 MSPS, supporting bearing-fault and gear-mesh analysis up to 50 kHz. Per the TI product page, the 69.6 dBFS SNR at 70 MHz input preserves bearing-tone spectral content, and the 86 dBc SFDR prevents bearing-tone harmonics from being masked by converter spurs. The four channels enable a single ADC to serve multiple sensors, reducing the PCB footprint of 8-slot industrial DAQ modules. The 1.8 V single-supply and 105 dB channel isolation simplify the analog front-end. The exposed-pad 48-VQFN package dissipates 800 mW; a 4-layer FR4 stack-up with EP ground plane is required.
Recommended
Recommended Products Summary
Engineering reference data for ADC34J24IRGZ25 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC34J25IRGZ25 | ADC34J24IRGZT | ADC34J24IRGZR | ADC34J25IRGZT | ADC34J24IRGZ25G4 | ADC3242IRGZ25 |
|---|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same |
| Resolution | 12 bit | 14 bit | 12 bit | 12 bit | 14 bit | 12 bit | 14 bit |
| Sample Rate | 125 MSPS | 125 MSPS | 160 MSPS | 125 MSPS | 160 MSPS | 125 MSPS | 125 MSPS |
| Number of Channels | 4 | 4 | 4 | 4 | 4 | 4 | 2 (per TI family datasheet) |
| Data Interface | JESD204B | JESD204B | JESD204B | JESD204B | JESD204B | JESD204B | LVDS |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Lifecycle Status | Obsolete | Obsolete (family) | Active (per TI family) | Active (per TI family) | Active (per TI family) | Obsolete (family) | Active |
Key Differentiators
- Pin-to-pin compatible with 14-bit ADC34J25 family for drop-in dynamic-range upgrade (vs ADC34J25IRGZ25)
- Higher sample rate than LVDS 12-bit competitors in the same 48-VQFN footprint (vs ADC3242IRGZ25)
- Lower power per channel than equivalent 14-bit JESD204B ADCs (vs ADC34J25IRGZ25)
Design Notes
The ADC34J24IRGZ25 operates from a single 1.8 V supply, but the 1.8 V AVDD rail is the most critical supply for noise performance. Use a low-noise LDO such as the TPS7A4700 to derive AVDD from a 5 V system rail; using a switching buck regulator directly on the 1.8 V rail risks 1-2 dB SNR degradation from switching noise coupling into the analog front-end. Decouple each AVDD pin with a 1 uF X7R ceramic + 0.1 uF X7R ceramic + 10 uF tantalum bulk cap placed within 5 mm of the supply pin. Keep the digital 1.8 V VDD1V8_DRV on a separate filter (10 ohm ferrite + 0.1 uF cap) to prevent digital switching noise from corrupting the analog supply.
At 125 MSPS the ADC34J24IRGZ25 dissipates approximately 800 mW total (200 mW per channel). The 48-VQFN exposed thermal pad must be soldered to a continuous ground plane on the top PCB layer, with at least 4 thermal vias (0.3 mm drill, 0.2 mm annular ring) directly under the EP for heat transfer to inner ground planes. Estimated: with a 4-layer 1 oz copper stack-up, theta_JA is approximately 25 C/W, so the junction rises 20 C above ambient at 800 mW - well within the 125 C max junction. For high-temperature environments (>70 C ambient), increase inner copper thickness to 2 oz or add forced-air cooling.
Layout for the ADC34J24IRGZ25 must follow 50-ohm controlled-impedance routing for the differential analog inputs (AINP/N) and the JESD204B lanes (JESD0P/N, JESD1P/N). Length-match the two JESD lanes within 0.1 mm of each other to keep lane-to-lane skew below 50 ps. Place the ADC within 50 mm of the FPGA to maintain JESD204B link margins; if the FPGA is further away, use pre-emphasis or a redriver. The exposed thermal pad (pin 48) must be soldered to a continuous top-layer ground pour with thermal vias - do not run traces under the EP, as this breaks the thermal path. Avoid routing digital signals (SPI, JESD lanes) under the analog input traces to prevent coupling.
Three common pitfalls with the ADC34J24IRGZ25: (1) Do not drive the analog inputs differentially below -2 dBFS at high input frequencies; the internal dither improves SFDR for small signals but cannot compensate for hard clipping. (2) SYSREF must be edge-aligned to the device clock (CLK_INP/N) per the JESD204B subclass 1 requirement; misalignment causes link-initialization failures. (3) The REF_CAP pin requires a 1 uF X7R capacitor to ground; do not omit it, as this is the internal reference decoupling node and the part will not function without it. (4) The RESETN pin must be held low at power-up until the 1.8 V rail stabilizes; releasing RESETN too early can leave the PLL in an undefined state.
The JESD204B interface of the ADC34J24IRGZ25 supports up to 4 Gbps per lane with the 160 MSPS family variant; for the 125 MSPS IRGZ25 speed bin, the lane rate is roughly 3.125 Gbps for a 2-lane configuration. Route the JESD lanes as 100-ohm differential pairs (85-ohm is acceptable) with length-matched P/N traces (intra-pair skew < 0.05 mm) and length-matched lane-to-lane (inter-lane skew < 0.5 mm). Use a continuous reference ground plane under the JESD lanes; do not route other signals between the differential pairs. If the link fails to initialize, verify the SYNC~ polarity, the SYSREF timing, and the lane-rate match between the ADC and the FPGA SERDES IP.
Compliance Information
RoHS compliant per TI product page. Halogen-free per TI's standard package materials for the RGZ VQFN. Not AEC-Q100 qualified - not designed for automotive safety-critical applications. Conflict-minerals compliant per TI's standard policy.
