ADC34J23IRGZ25 - Quad 12-bit 80MSPS ADC | Texas Instruments
MPN: ADC34J23IRGZ25 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.65 | $256.50 |
| 100 | $22.8 | $2,280.00 |
| 500 | $20.2 | $10,100.00 |
| 1,000 | $17.5 | $17,500.00 |
ADC34J23IRGZ25 Overview
An ADC (analog-to-digital converter) is a data-converter IC that translates real-world analog signals into discrete digital codes for processing by FPGAs, ASICs, microcontrollers, or DSPs. Pipeline ADCs in particular are favored for sample rates between a few MSPS and several hundred MSPS because they combine high throughput with low per-channel power. The ADC34J23 sits at the interface layer of any signal chain — between analog signal-conditioning (amplifiers, filters, drivers) and the digital domain (FPGA, processor, JESD204B/C link, or LVDS bus). Industry synonyms include "high-speed ADC," "IF-sampling ADC," and "digitizer IC."
Key specifications include 12-bit resolution, 80 MSPS maximum sampling rate (configurable 50 to 160 MSPS across the family), four simultaneous sampled inputs, pipelined architecture for low latency, low-voltage differential signal (LVDS) digital interface to the host FPGA, and a 1.8 V analog supply. Each channel achieves excellent linearity across the industrial temperature range, and the integrated input buffer simplifies front-end design.
The architecture combines four pipelined core ADCs with on-chip reference and timing-generation circuits, enabling software-configurable sample rates, channel-power scaling, and test-pattern injection. The device supports both internal and external reference operation, allowing designers to optimize drift performance versus BOM count.
Typical applications include multi-antenna wireless base-station receivers, radar and phased-array digitizers, cable-infrastructure head-ends, ultrasound and other medical imaging front-ends, and automated test equipment (ATE). The four matched channels also suit multi-axis vibration or current-sensing systems in industrial monitoring.
When designing with the ADC34J23, match the LVDS trace lengths on the digital bus to within short skew budgets and provide a clean 1.8 V analog LDO, such as the TPS7A47 family, on each AVDD pin to preserve SNR. Use the device's power-down modes between acquisitions in low-duty-cycle applications to reduce dissipation.
This page synthesizes distributor inventory, drop-in alternative MPNs, and practical layout guidance not assembled in the manufacturer datasheet alone.
Drop-in alternatives for ADC34J23IRGZ25 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC34J23IRGZ25 (same form factor and footprint) — differing in Package, Number of Channels, Input Type, Resolution, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC34J24IRGZ25
✅ Drop-In✓ In Stock
$26.75 / Unit
View Datasheet →ADC34J25IRGZ25
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View Datasheet →ADC3423IRTQ25
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$21.85 / Unit
View Datasheet →ADC32J44IRGZ25
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View Datasheet →ADS62P23IRGC25
✅ Drop-In✓ In Stock
$18.85 / Unit
View Datasheet →AD9629XCPZ-40
✅ Drop-In✓ In Stock
$7.45 / Unit
View Datasheet →ADC34J23IRGZ25 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bit |
| Sample Rate (max) | 80 MSPS |
| Number of Input Channels | 4 |
| Architecture | Pipelined |
| Input Type | Differential |
| Analog Supply Voltage | 1.8 V |
| Digital I/O Supply | 1.8 V to 3.3 V |
| Digital Interface | LVDS |
| Package | 48-VQFN (RGZ), 7x7 mm |
| Number of Pins | 48 |
| Operating Temperature Range | -40 C to +85 C (Industrial) |
| Reference Type | Internal / External |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead Free | Yes |
ADC34J23IRGZ25 Pin Configuration
| Pin 1 | AINP_A — Channel A positive analog input |
| Pin 2 | AINM_A — Channel A negative analog input |
| Pin 3 | AVDD — 1.8 V analog supply |
| Pin 4 | AVSS — Analog ground |
| Pin 5 | AINP_B — Channel B positive analog input |
| Pin 6 | AINM_B — Channel B negative analog input |
| Pin 7 | AVDD — 1.8 V analog supply |
| Pin 8 | AVSS — Analog ground |
| Pin 9 | AINP_C — Channel C positive analog input |
| Pin 10 | AINM_C — Channel C negative analog input |
| Pin 11 | AVDD — 1.8 V analog supply |
| Pin 12 | AVSS — Analog ground |
| Pin 13 | AINP_D — Channel D positive analog input |
| Pin 14 | AINM_D — Channel D negative analog input |
| Pin 15 | AVDD — 1.8 V analog supply |
| Pin 16 | AVSS — Analog ground |
| Pin 17 | VCM — Common-mode voltage output for analog inputs |
| Pin 18 | REFT — Reference decoupling top pin |
| Pin 19 | REFB — Reference decoupling bottom pin |
| Pin 20 | REFRES — External reference resistor |
| Pin 21 | AVDD — 1.8 V analog supply |
| Pin 22 | AVSS — Analog ground |
| Pin 23 | SENSE — Reference mode select (internal/external) |
| Pin 24 | RESET — Hardware reset (active low) |
| Pin 25 | PDN — Power-down input |
| Pin 26 | SYNC — LVDS synchronization input |
| Pin 27 | CLKP — Positive clock input |
| Pin 28 | CLKM — Negative clock input |
| Pin 29 | AVDD — 1.8 V analog supply |
| Pin 30 | AVSS — Analog ground |
| Pin 31 | DVDD — Digital supply |
| Pin 32 | DVSS — Digital ground |
| Pin 33 | D0P — LVDS data output 0 positive |
| Pin 34 | D0M — LVDS data output 0 negative |
| Pin 35 | D1P — LVDS data output 1 positive |
| Pin 36 | D1M — LVDS data output 1 negative |
| Pin 37 | D2P — LVDS data output 2 positive |
| Pin 38 | D2M — LVDS data output 2 negative |
| Pin 39 | D3P — LVDS data output 3 positive |
| Pin 40 | D3M — LVDS data output 3 negative |
| Pin 41 | DCLKP — LVDS clock output positive |
| Pin 42 | DCLKM — LVDS clock output negative |
| Pin 43 | DRDY — Data ready LVDS output |
| Pin 44 | DVDD — Digital supply |
| Pin 45 | DVSS — Digital ground |
| Pin 46 | SEN — Serial interface enable |
| Pin 47 | SCLK — Serial interface clock |
| Pin 48 | SDATA — Serial interface data |
Typical Applications
ADC34J23IRGZ25 is suitable for 6 applications: Multi-Antenna Wireless Base Station Receiver, Phased-Array Radar / Phase-Coherent Digitizer, Medical Ultrasound Beamforming Front-End, Automated Test Equipment (ATE) Waveform Digitizer, Industrial Multi-Axis Vibration Monitoring, Cable Infrastructure / QAM Demodulation Head-End.
Multi-Antenna Wireless Base Station Receiver
The ADC34J23IRGZ25's four matched 12-bit 80-MSPS sampling channels provide simultaneous digitization of multiple receiver paths in LTE and 5G NR base-station applications. Channel-to-channel gain and phase matching are essential for the MIMO and beamforming digital signal processing performed in the FPGA fabric downstream. The integrated LVDS interface delivers the four channels directly into FPGA transceivers without requiring external glue logic, simplifying board layout.
Recommended
Phased-Array Radar / Phase-Coherent Digitizer
In active phased-array radar and direction-finding systems, the ADC34J23IRGZ25 simultaneously samples element-channel IF outputs, preserving inter-channel phase coherence required for digital beamforming. The 12-bit resolution and pipelined latency are well-matched to a 40-200 MHz intermediate frequency, where SNR of 65-70 dB is acceptable for target detection. Designers select this ADC for its deterministic sample timing, low inter-channel skew, and ability to drive an LVDS bus into FPGA sample FIFOs.
Recommended
Medical Ultrasound Beamforming Front-End
Ultrasound imaging arrays require tens to hundreds of synchronized receive channels, and the ADC34J23IRGZ25's quad-channel 12-bit 80-MSPS design fits compact multi-channel pre-beamformer boards. The 1.8 V analog supply minimizes per-channel dissipation, which is critical for dense probe-head PCBs with limited thermal headroom. The LVDS interface connects to local FPGAs that perform per-channel time-gain compensation, envelope detection, and partial beamforming summation.
Recommended
Automated Test Equipment (ATE) Waveform Digitizer
In ATE pin-electronics cards and modular instrumentation, the ADC34J23IRGZ25 captures 12-bit, 80-MSPS snapshots of multi-pin waveforms for go/no-go measurement. The four channels allow a single ADC to digitize the stimulus, response, and two reference nodes in parallel, reducing measurement latency and improving correlation. Low deterministic latency of the pipelined core makes the part attractive for round-trip trigger measurement on high-speed buses.
Recommended
Industrial Multi-Axis Vibration Monitoring
The ADC34J23IRGZ25 simultaneously samples vibration sensors mounted on rotating shafts, gearboxes, and structural members, supporting condition-monitoring systems in predictive maintenance applications. Four channels per chip let one ADC service an X-Y-Z accelerometer plus a tachometer or microphone reference channel, simplifying isolation-barrier crossings and minimizing per-channel cost. Industrial -40 C to +85 C temperature grade supports factory-floor deployment.
Recommended
Cable Infrastructure / QAM Demodulation Head-End
DOCSIS and digital-video head-end equipment rely on dense multi-channel digitization of intermediate-frequency signals from optical receivers and RF tuners. The ADC34J23IRGZ25 digitizes four adjacent channels at 80 MSPS with 12-bit resolution, sufficient to resolve dense QAM constellations. The combination of low-voltage differential signaling, integrated input buffer, and small 7x7 mm footprint simplifies dense modulator-board design.
Recommended
Recommended Products Summary
Engineering reference data for ADC34J23IRGZ25 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC34J24IRGZ25 | ADC34J25IRGZ25 | ADS62P23IRGC25 | AD9629XCPZ-40 |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Analog Devices |
| Package | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGC) - same footprint class | 48-LFCSP (XCP) - same pitch |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Sample Rate (max) | 80 MSPS | 105 MSPS | 125 MSPS | 80 MSPS | 40 MSPS |
| Number of Channels | 4 | 4 | 4 | 2 | 4 |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Digital Interface | LVDS | LVDS | LVDS | LVDS | LVDS |
| Analog Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
Key Differentiators
- Four simultaneous matched sample channels in one chip (vs ADS62P23IRGC25)
- Higher maximum sample rate than lower-tier family members (vs AD9629XCPZ-40)
- Lower-power option than the 125 MSPS cousin (vs ADC34J25IRGZ25)
Design Notes
Route the LVDS D0/D1/D2/D3 and DCLK pairs as tightly length-matched differential traces, ideally with 100-ohm differential impedance and 0.1 lambda matching tolerance. Keep the digital traces on inner layers and shield them with continuous ground pours to minimize edge coupling from the analog inputs. Pin 1 is located at the dot marker on the package, and the exposed pad at center must be soldered to a continuous, low-inductance thermal pad tied to AVSS on at least six vias for thermal and electrical grounding.
Decouple each AVDD pin with a 100 nF X7R ceramic plus a 10 uF bulk capacitor placed within 5 mm of the pins. Use a ferrite bead between the 1.8 V analog and 1.8 V digital supplies to break high-frequency ground loops. The VCM pin (pin 17) must be bypassed with at least 1 uF to AVSS to provide a clean reference for the input common-mode. The TPS7A4701 LDO or similar low-noise regulator is well-matched to supply this ADC's analog rail.
Clock the ADC with a low-jitter differential source — total jitter above 200 fs_RMS will degrade SNR more than the device's analog front-end noise. Terminate the CLKP/CLKM pins at the package with 100-ohm differential. For multi-ADC synchronization in beamforming arrays, share a common low-jitter clock and use the SYNC input (pin 26) to align divider state and reset deterministic pipeline latencies.
Estimated: The ADC's four channels are designed for differential, AC-coupled inputs; if DC-coupling is required, ensure the upstream driver can sit at the VCM common-mode and never exceed AVDD + 0.3 V at the inputs. Bypassing or omitting the REFRES pin changes the internal reference scale and significantly affects gain error, so leave the external reference resistor installed as recommended in the datasheet.
Compliance Information
RoHS and lead-free compliant per TI product page. Not AEC-Q100 qualified — for automotive grade, contact TI for the ADC34J2x-Q1 variant. Halogen-free status not stated in verified web data.
