ADS5547IRGZ25 - 14-Bit 210 MSPS ADC with DDR LVDS/CMOS | Texas Instruments
MPN: ADS5547IRGZ25 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.65 | $346.50 |
| 100 | $30.8 | $3,080.00 |
| 500 | $27.5 | $13,750.00 |
| 1,000 | $24.5 | $24,500.00 |
ADS5547IRGZ25 Overview
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog input signals and converts them into discrete digital codes at a defined sample rate. High-speed ADCs sit at the front end of digital signal processing chains in communications, radar, instrumentation, and test equipment, where they translate real-world analog waveforms into binary data that an FPGA, ASIC, or DSP can process. Within the broader IC taxonomy, this part belongs to data-conversion ICs, an ADC family, and more specifically a pipelined ADC architecture chosen for sample rates from 100 MSPS to several hundred MSPS.
Key performance specifications include 73.3 dBFS signal-to-noise ratio (SNR) at intermediate frequencies, 85 dBc spurious-free dynamic range (SFDR) at a 70 MHz IF input with 0 dB gain, no missing codes across the full 14-bit range, and a DDR LVDS interface that doubles data throughput per output pin. The device includes an internal reference with optional external-reference mode for gain or system-level calibration.
The architecture is a multi-stage pipelined converter with on-chip sample-and-hold and digital error correction. Each stage resolves a subset of bits; residue is passed forward with redundancy for digital correction, allowing high sample rates while preserving linearity. The DDR LVDS output bus lets the FPGA capture both data transitions per clock, easing board-level timing closure.
Typical applications include multi-carrier wireless base-station receivers, radar and electronic-warfare front ends, medical imaging systems, and high-speed data acquisition cards for test and measurement. The 800 MHz analog input bandwidth enables direct IF sampling, eliminating an analog downconversion stage. Industrial-grade -40C to +85C operation supports outdoor and factory-floor deployment. When laying out a PCB for this converter, keep analog and digital grounds separated under the package and route the DDR LVDS pairs with controlled 100 ohm differential impedance. The exposed thermal pad must be soldered to a continuous ground plane to keep junction temperature within safe limits at 1.23 W continuous dissipation.
Drop-in alternatives for ADS5547IRGZ25 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADS5547IRGZ25 (same form factor and footprint) — differing in Input Type, Missing Codes, Operating Temperature Range, Output Interface, Package.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADS5547IRGZR
✅ Drop-In📋 Reference alternative (not in catalog)
ADS5547IRGZT
✅ Drop-In📋 Reference alternative (not in catalog)
ADS6149IRGZT
✅ Drop-In📋 Reference alternative (not in catalog)
ADS6129IRGZT
✅ Drop-In📋 Reference alternative (not in catalog)
ADS5547IRGZ25 Maximum Ratings & Electrical Characteristics
| Resolution | 14 bits |
| Sample Rate (Maximum) | 210 MSPS |
| Architecture | Pipelined |
| Number of Inputs | 1 |
| Input Type | Single-ended analog |
| Analog Input Bandwidth | 800 MHz |
| SNR | 73.3 dBFS at IF |
| SFDR | 85 dBc at 70 MHz IF, 0 dB gain |
| Output Interface | DDR LVDS or CMOS, user-selectable |
| Output Format | Parallel |
| Total Power Dissipation | 1.23 W |
| Internal Sample-and-Hold | Yes |
| Reference | Internal, with external-reference mode supported |
| Missing Codes | None (14-bit no-missing-codes guaranteed) |
| Supply Voltage | 3.3 V |
| Operating Temperature Range | -40C to +85C (industrial) |
| Package | 48-pin VQFN (RGZ) 7x7 mm with exposed thermal pad |
| Mounting Type | Surface Mount |
| MSL Level | 3 |
| RoHS Status | Compliant |
ADS5547IRGZ25 Pin Configuration
| Pin 1 | AVDD — Analog supply voltage (3.3 V) |
| Pin 2 | GND — Ground |
| Pin 3 | INP — Analog positive input |
| Pin 4 | INN — Analog negative input |
| Pin 5 | VCM — Common-mode voltage output |
| Pin 6 | REF — Reference voltage bypass |
| Pin 7 | AVDD — Analog supply voltage (3.3 V) |
| Pin 8 | GND — Ground |
| Pin 9 | CLK — Clock input |
| Pin 10 | CLKB — Complementary clock input |
| Pin 11 | GND — Ground |
| Pin 12 | DRVDD — Digital output supply (3.3 V or 1.8 V) |
| Pin 13 | D0+/D0 — LVDS/CMOS data output bit 0 |
| Pin 14 | D0- — LVDS complementary bit 0 |
| Pin 15 | D1+/D1 — LVDS/CMOS data output bit 1 |
| Pin 16 | D1- — LVDS complementary bit 1 |
| Pin 17 | D2+/D2 — LVDS/CMOS data output bit 2 |
| Pin 18 | D2- — LVDS complementary bit 2 |
| Pin 19 | D3+/D3 — LVDS/CMOS data output bit 3 |
| Pin 20 | D3- — LVDS complementary bit 3 |
| Pin 21 | D4+/D4 — LVDS/CMOS data output bit 4 |
| Pin 22 | D4- — LVDS complementary bit 4 |
| Pin 23 | D5+/D5 — LVDS/CMOS data output bit 5 |
| Pin 24 | D5- — LVDS complementary bit 5 |
| Pin 25 | D6+/D6 — LVDS/CMOS data output bit 6 |
| Pin 26 | D6- — LVDS complementary bit 6 |
| Pin 27 | D7+/D7 — LVDS/CMOS data output bit 7 |
| Pin 28 | D7- — LVDS complementary bit 7 |
| Pin 29 | DRVDD — Digital output supply |
| Pin 30 | GND — Ground |
| Pin 31 | D8+/D8 — LVDS/CMOS data output bit 8 |
| Pin 32 | D8- — LVDS complementary bit 8 |
| Pin 33 | D9+/D9 — LVDS/CMOS data output bit 9 |
| Pin 34 | D9- — LVDS complementary bit 9 |
| Pin 35 | D10+/D10 — LVDS/CMOS data output bit 10 |
| Pin 36 | D10- — LVDS complementary bit 10 |
| Pin 37 | D11+/D11 — LVDS/CMOS data output bit 11 |
| Pin 38 | D11- — LVDS complementary bit 11 |
| Pin 39 | D12+/D12 — LVDS/CMOS data output bit 12 |
| Pin 40 | D12- — LVDS complementary bit 12 |
| Pin 41 | D13+/D13 — LVDS/CMOS data output bit 13 |
| Pin 42 | D13- — LVDS complementary bit 13 |
| Pin 43 | DRVDD — Digital output supply |
| Pin 44 | GND — Ground |
| Pin 45 | OE — Output enable |
| Pin 46 | RESET — Reset input |
| Pin 47 | CS — Chip select / serial interface |
| Pin 48 | SCLK — Serial clock |
Typical Applications
ADS5547IRGZ25 is suitable for 6 applications: Wireless Base-Station Receiver, Radar and Electronic-Warfare Front End, Medical Imaging Systems, High-Speed Data Acquisition Cards, Software Defined Radio (SDR) Platforms, Industrial Automation Test Equipment.
Wireless Base-Station Receiver
The ADS5547IRGZ25 is well-suited for multi-carrier wireless base-station receivers where direct IF-sampling of the radio signal chain is required. Its 800 MHz analog input bandwidth allows digitization of IF signals at 70 MHz or higher without an analog downconversion stage, while 73.3 dBFS SNR and 85 dBc SFDR ensure the wide-band receiver preserves small-signal fidelity in the presence of large blocking signals. The 210 MSPS sample rate supports symbol-rate processing of multi-carrier LTE and 5G NR signals. Power dissipation of 1.23 W is acceptable for the receiver card; the DDR LVDS interface simplifies routing to the FPGA baseband processor. Place the ADC close to the FPGA with controlled-impedance differential pairs to maintain signal integrity.
Recommended
Radar and Electronic-Warfare Front End
The ADS5547IRGZ25 fits radar and electronic-warfare (EW) receiver front ends that demand wide analog bandwidth and high spurious-free dynamic range. The 800 MHz input bandwidth supports direct sampling of IF signals from radar receivers, preserving phase and amplitude information needed for pulse-compression algorithms. SFDR of 85 dBc at 70 MHz IF ensures that small targets remain detectable in the presence of large clutter returns. The 14-bit resolution and 210 MSPS sample rate provide the dynamic range and time resolution required for synthetic-aperture radar (SAR) and EW warning receivers. DDR LVDS output pairs reduce the number of board traces needed to deliver 14-bit words at 210 MHz word rate to the FPGA processor.
Recommended
Medical Imaging Systems
The ADS5547IRGZ25 is used in medical imaging front ends such as ultrasound beamformers and PET detector readout boards. Ultrasound requires 12 to 14-bit resolution at 40 to 200 MSPS to capture RF echo signals from piezoelectric transducers. The ADS5547IRGZ25's low power dissipation (1.23 W) is critical for portable and cart-based ultrasound systems where thermal management is constrained. The 73.3 dBFS SNR preserves the dynamic range needed for harmonic imaging modes. For PET readout, the 800 MHz input bandwidth allows direct sampling of detector pulses without an analog shaping amplifier, simplifying the analog signal chain.
Recommended
High-Speed Data Acquisition Cards
The ADS5547IRGZ25 is a strong fit for high-speed data acquisition cards used in test and measurement instrumentation, including oscilloscopes, spectrum analyzers, and protocol analyzers. The 210 MSPS sample rate supports digitizing signals up to approximately 100 MHz in the first Nyquist zone without aliasing. The 800 MHz input bandwidth extends the usable bandwidth into the second and third Nyquist zones for IF digitizing applications. The DDR LVDS output mode enables direct connection to high-pin-count FPGAs without requiring an external serializer. The CMOS output mode can be used for slower designs that prefer single-ended bus signaling.
Recommended
Software Defined Radio (SDR) Platforms
The ADS5547IRGZ25 supports wideband software-defined radio (SDR) platforms that digitize RF signals directly for software-based demodulation. The 800 MHz analog bandwidth allows direct sampling of HF, VHF, and low-UHF signals, while 73.3 dBFS SNR ensures that wideband digitized signals maintain adequate signal-to-noise ratio for digital filtering and demodulation. The 210 MSPS sample rate provides sufficient oversampling for typical SDR applications up to approximately 70 MHz of instantaneous bandwidth. The DDR LVDS output minimizes FPGA pin count in multi-channel SDR receiver arrays. Industrial temperature range supports outdoor and vehicular SDR deployments.
Recommended
Industrial Automation Test Equipment
The ADS5547IRGZ25 serves industrial automation test equipment that requires high-speed, high-resolution analog capture with industrial-grade temperature rating. Applications include motor-drive analyzers, power-quality monitors, and factory-automation signal analyzers. The -40C to +85C operating range supports deployment in factory-floor enclosures without additional thermal management. The 1.23 W typical power dissipation is acceptable for sealed industrial test equipment where convection cooling is limited. The DDR LVDS output interface connects directly to industrial FPGAs or processors for real-time waveform analysis. The pipelined architecture provides deterministic latency for closed-loop test applications.
Recommended
Recommended Products Summary
Engineering reference data for ADS5547IRGZ25 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADS5547IRGZR | ADS5547IRGZT | ADS6149IRGZT | ADS6129IRGZT |
|---|---|---|---|---|---|
| Package | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) - same | 48-VQFN (RGZ) - same | 48-VQFN (RGZ) - same | 48-VQFN (RGZ) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 14 bits | 14 bits | 14 bits | 14 bits | 12 bits |
| Sample Rate (Maximum) | 210 MSPS | 210 MSPS | 210 MSPS | 250 MSPS | 250 MSPS |
| Analog Input Bandwidth | 800 MHz | 800 MHz | 800 MHz | 450 MHz (typical for ADS614x family) | 450 MHz (typical for ADS614x family) |
| SNR | 73.3 dBFS at IF | 73.3 dBFS at IF | 73.3 dBFS at IF | 74 dBFS at 10 MHz | 70 dBFS at 10 MHz |
| SFDR | 85 dBc at 70 MHz IF | 85 dBc at 70 MHz IF | 85 dBc at 70 MHz IF | 82 dBc at 70 MHz IF | 82 dBc at 70 MHz IF |
| Output Interface | DDR LVDS / CMOS parallel | DDR LVDS / CMOS parallel | DDR LVDS / CMOS parallel | DDR LVDS / CMOS parallel | DDR LVDS / CMOS parallel |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Key Differentiators
- Higher analog input bandwidth than the ADS6149IRGZT (vs ADS6149IRGZT)
- Higher SFDR at 70 MHz IF than the ADS6149IRGZT (vs ADS6149IRGZT)
- Higher resolution than the ADS6129IRGZT (vs ADS6129IRGZT)
Design Notes
Use a four-layer PCB with continuous ground planes on layers 2 and 4. Place input capacitors within 5 mm of the analog supply pins (AVDD). Route the clock input (CLK/CLKB) as a 100 ohm differential pair from the clock driver with length matching to within 2 ps. Separate analog (AVDD) and digital (DRVDD) ground returns under the package to avoid digital noise coupling into the analog front end. The exposed thermal pad must be soldered to a continuous ground plane with at least 16 thermal vias to keep junction temperature rise below 10C at 1.23 W dissipation.
The DDR LVDS output pairs should be routed as 100 ohm differential microstrip or stripline with length matching within 20 ps across all 14 bits. Use AC-coupling capacitors in series with each LVDS pair if the receiver uses a different common-mode voltage than the ADC. For CMOS output mode, route single-ended data lines with 50 ohm characteristic impedance and place a 22 ohm series damping resistor at the driver output to control ringing. Match clock-to-data trace lengths within 50 ps for the LVDS interface.
Estimated: with 1.23 W dissipation, junction-to-ambient thermal resistance of approximately 30 C/W for the 48-VQFN (RGZ) with proper board layout (per TI datasheet package thermal data), the junction temperature rise above ambient is about 37 C. At an industrial ambient maximum of 85C, junction temperature reaches approximately 122C, which is below the 150C TJmax. For sealed enclosures with limited airflow, add thermal vias and copper pours to keep TJ below 125C. The exposed pad must be soldered to a continuous ground plane to achieve the package thermal resistance rating.
Do not float the unused analog input (INP or INN) when running in single-ended mode; tie it to VCM through a 1 nF capacitor to avoid charge-kickback noise. Do not apply a clock signal before power is stable; power sequencing (AVDD before DRVDD) is recommended. When switching from internal to external reference mode, allow at least 100 ms for the reference buffer to settle before initiating a conversion. Verify the SCLK and CS timing in the serial-interface configuration section before the first reset to avoid lockup of the configuration registers.
Power AVDD and DRVDD from separate low-noise LDO regulators to prevent digital switching noise from coupling into the analog supply. According to the TI datasheet, the AVDD supply should have less than 10 mVpp ripple in the band from 10 kHz to 100 MHz. Place 10 uF bulk capacitors and 0.1 uF decoupling capacitors within 2 mm of each AVDD and DRVDD pin. Use ferrite beads in series with each AVDD pin if power-supply conducted noise is a concern in the system.
Compliance Information
RoHS compliant per TI product page. Industrial temperature grade (-40C to +85C). Not AEC-Q100 qualified; for automotive applications, contact TI about the ADS5547 family automotive-grade options.
