ADS6244IRGZ25 - Dual 14-Bit 105MSPS Serial LVDS ADC | Texas Instruments
MPN: ADS6244IRGZ25 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $42.5 | $42.50 |
| 10 | $38.25 | $382.50 |
| 100 | $33.9 | $3,390.00 |
| 500 | $29.75 | $14,875.00 |
| 1,000 | $26.4 | $26,400.00 |
ADS6244IRGZ25 Overview
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous analog voltages into discrete digital codes at a specified sample rate. The ADS6244 belongs to the high-speed pipeline ADC class, which excels at sampling IF/RF signals in the 1-100+ MHz range with 10-16 bit resolution. Within TI's power-management and data-converter hierarchy, the ADS6244 sits as a precision signal-chain component, frequently paired with low-noise LDOs, differential amplifiers, and FPGA/ASIC LVDS receivers to build complete digital signal acquisition subsystems.
The ADS6244's serialized LVDS interface reduces board trace count by 6x compared to parallel CMOS outputs, simplifying PCB routing and lowering EMI in dense multi-channel systems. The integrated sample-and-hold and internal reference eliminate the need for external reference decoupling, reducing BOM cost. Programmable gain allows system designers to optimize spurious-free dynamic range (SFDR) versus signal-to-noise ratio (SNR) at the system level without external attenuators. Per TI documentation, the device is part of a pin-compatible 12-bit family (ADS622X) and a feature-compatible quad-channel family (ADS642X/ADS644X), enabling board reuse across performance tiers.
The architecture is a multi-stage pipeline with per-stage error correction, supporting 14-bit no-missing-codes performance at the full 105 MSPS rate. Built-in self-test patterns, a serial peripheral interface (SPI) for mode configuration, and integrated LVDS termination simplify FPGA interface design. The 48-VQFN package with exposed thermal pad achieves 31.4 C/W theta_JA, adequate for industrial temperature operation at -40C to +85C.
Typical applications include medical imaging ultrasound receivers, communications IF/baseband digitizers, multi-channel software-defined radio (SDR) platforms, industrial vibration analysis, and high-speed test and measurement instrumentation. In each case, the dual-channel architecture saves PCB area versus two discrete ADCs and the LVDS interface minimizes FPGA pin count.
When designing with the ADS6244IRGZ25, allocate adequate copper pour under the exposed pad and decouple AVDD/DVDD with 0.1 uF ceramic capacitors placed within 5 mm of each supply pin. The serialized LVDS data rate reaches 595 Mbps per channel at 105 MSPS - verify FPGA LVDS receiver capabilities and PCB controlled-impedance (100 ohm differential) routing before final layout.
This page synthesizes distributor pricing, pin-compatible same-family variants, and application-specific design guidance beyond the manufacturer datasheet, enabling faster BOM decisions for dual-channel 105 MSPS designs.
Drop-in alternatives for ADS6244IRGZ25 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADS6244IRGZ25 (same form factor and footprint) — differing in Package, Resolution, Operating Temperature Range, Input Type, Analog Supply Voltage.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADS6245IRGZ25
✅ Drop-In📋 Reference alternative (not in catalog)
ADS6244IRGZT
✅ Drop-In📋 Reference alternative (not in catalog)
ADS6242IRGZR
✅ Drop-In✓ In Stock
$18.25 / Unit
View Datasheet →ADS6129IRGZ25
✅ Drop-In✓ In Stock
$23.1 / Unit
View Datasheet →ADS61B29IRGZ25
✅ Drop-In✓ In Stock
$17.8 / Unit
View Datasheet →ADS6244IRGZ25 Maximum Ratings & Electrical Characteristics
| Resolution | 14 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sample Rate (max) | 105 MSPS |
| Architecture | Pipelined |
| Input Type | Differential |
| Output Interface | Serialized LVDS |
| Analog Supply Voltage | 3.3 V |
| Digital Supply Voltage | 3.3 V |
| Minimum Input Amplitude | 400 mVpp |
| Programmable Gain | 3.5 dB coarse + up to 6 dB fine |
| Reference | Internal (external reference supported) |
| Operating Temperature Range | -40C to +85C |
| Package | 48-pin VQFN (RGZ) 7x7 mm with exposed pad |
| Package Code | HVQCCN (No-Lead) |
| Mounting Type | Surface Mount |
| Pin-Compatible Family | 12-bit ADS622X; quad-channel ADS642X/ADS644X |
ADS6244IRGZ25 Pin Configuration
| Pin 1 | AVDD — Analog 3.3 V supply |
| Pin 2 | AVSS — Analog ground |
| Pin 3 | INP_A — Channel A positive differential input |
| Pin 4 | INN_A — Channel A negative differential input |
| Pin 5 | AVDD — Analog 3.3 V supply |
| Pin 6 | AVSS — Analog ground |
| Pin 7 | INP_B — Channel B positive differential input |
| Pin 8 | INN_B — Channel B negative differential input |
| Pin 9 | AVDD — Analog 3.3 V supply |
| Pin 10 | AVSS — Analog ground |
| Pin 11 | VCM — Common-mode voltage output (1.5 V) |
| Pin 12 | REF — Reference voltage pin (internal/external select) |
| Pin 13 | AVSS — Analog ground |
| Pin 14 | AVDD — Analog 3.3 V supply |
| Pin 15 | NC — Not connected |
| Pin 16 | AVDD — Analog 3.3 V supply |
| Pin 17 | AVSS — Analog ground |
| Pin 18 | SCLK — SPI clock input |
| Pin 19 | SDOUT — SPI serial data output |
| Pin 20 | SDATA — SPI serial data input |
| Pin 21 | SEN — SPI enable (active low) |
| Pin 22 | RESET — Hardware reset (active low) |
| Pin 23 | PDN — Power-down (active high) |
| Pin 24 | AVSS — Analog ground |
| Pin 25 | AVDD — Analog 3.3 V supply |
| Pin 26 | CLKP — Differential clock input positive |
| Pin 27 | CLKN — Differential clock input negative |
| Pin 28 | AVSS — Analog ground |
| Pin 29 | AVDD — Analog 3.3 V supply |
| Pin 30 | OUTCLK_P — LVDS output clock positive |
| Pin 31 | OUTCLK_N — LVDS output clock negative |
| Pin 32 | DVDD — Digital 3.3 V supply |
| Pin 33 | DVSS — Digital ground |
| Pin 34 | D0_P — LVDS data output channel A positive |
| Pin 35 | D0_N — LVDS data output channel A negative |
| Pin 36 | D1_P — LVDS data output channel B positive |
| Pin 37 | D1_N — LVDS data output channel B negative |
| Pin 38 | DVDD — Digital 3.3 V supply |
| Pin 39 | DVSS — Digital ground |
| Pin 40 | DVDD — Digital 3.3 V supply |
| Pin 41 | DVSS — Digital ground |
| Pin 42 | NC — Not connected |
| Pin 43 | NC — Not connected |
| Pin 44 | DVDD — Digital 3.3 V supply |
| Pin 45 | DVSS — Digital ground |
| Pin 46 | NC — Not connected |
| Pin 47 | NC — Not connected |
| Pin 48 | NC — Not connected |
Typical Applications
ADS6244IRGZ25 is suitable for 6 applications: Medical Ultrasound Receiver Array, Communications IF/Baseband Digitizer, Multi-Channel Software-Defined Radio (SDR), Industrial Vibration & Acoustic Analysis, High-Speed Test & Measurement Instrumentation, Phased-Array Radar & Beamforming Receivers.
Medical Ultrasound Receiver Array
The ADS6244IRGZ25's dual simultaneous-sampling 14-bit 105 MSPS architecture with serialized LVDS output is well-suited to multi-channel medical ultrasound receiver arrays. Each ultrasound channel requires I/Q demodulation followed by simultaneous baseband sampling; the ADS6244's two matched sample-and-hold stages preserve channel-to-channel phase coherence essential for beamforming and Doppler processing. With 14-bit resolution the device delivers approximately 74 dBFS SNR at 105 MSPS, sufficient to resolve subtle tissue echogenicity differences. The serialized LVDS interface reduces the cable count between the probe head and the processing FPGA by a factor of 6x compared to parallel CMOS ADCs - a critical advantage when routing 64-256 channels in a compact cart-based ultrasound system. Internal reference and programmable fine gain (up to 6 dB) let the designer optimize SFDR for harmonic imaging versus SNR for B-mode grayscale.
Recommended
Communications IF/Baseband Digitizer
In communications IF/baseband signal chains the ADS6244IRGZ25 captures I/Q signal pairs at baseband or low IF (typically 0-70 MHz) at 105 MSPS, providing 14-bit quantization for narrowband cellular, software-defined radio, and wireless infrastructure receivers. Each channel's differential input handles amplitudes down to 400 mVpp, simplifying the interface from the preceding mixer/filter stage and reducing LO leakage sensitivity. The serialized LVDS output delivers both I and Q streams over a single differential pair per channel, easing FPGA pin allocation in multi-antenna MIMO receivers. The 3.5 dB coarse gain plus 6 dB fine gain programmability enables the system designer to trade SFDR (for blocker rejection) against sensitivity (for low-SNR edge-of-coverage operation) without board changes - a key advantage over fixed-gain ADCs that require external attenuators.
Recommended
Multi-Channel Software-Defined Radio (SDR)
Multi-channel SDR platforms benefit from the ADS6244IRGZ25's two simultaneous-sampling channels and serialized LVDS output, enabling dense antenna arrays or phased-array receivers in a compact footprint. At 105 MSPS per channel the device captures 50 MHz of instantaneous bandwidth per channel, sufficient for wideband HF/VHF/UHF monitoring, spectrum sensing, and direction-finding applications. The dual-channel architecture halves PCB area versus two discrete single-channel ADCs while preserving sub-sample timing accuracy critical for phase-coherent beamforming. The 48-VQFN 7x7 mm package with exposed thermal pad allows stacking multiple ADS6244 devices in a tiled array - e.g. 8 ADS6244s provide 16 channels with synchronized LVDS framing - enabling cost-effective multi-channel SDR without migrating to larger quad-channel ADC packages.
Recommended
Industrial Vibration & Acoustic Analysis
For industrial vibration monitoring, modal analysis, and acoustic emission testing, the ADS6244IRGZ25's dual-channel 14-bit 105 MSPS performance captures high-frequency accelerometer and microphone signals with sufficient dynamic range to resolve small-amplitude faults. The simultaneous sampling across two channels enables differential measurement configurations - e.g. capturing both an accelerometer and a reference tacho probe simultaneously for order-tracking analysis. The 14-bit resolution yields approximately 74 dBFS SNR, suitable for FFT-based spectral analysis where spurious-free dynamic range (SFDR) of 85+ dBc enables clean identification of bearing defect frequencies. The 48-VQFN industrial-grade (-40C to +85C) package supports factory-floor deployment, and the serialized LVDS output keeps cable and connector costs low in distributed sensor networks.
Recommended
High-Speed Test & Measurement Instrumentation
Bench-top oscilloscopes, spectrum analyzers, and digitizers benefit from the ADS6244IRGZ25's 14-bit 105 MSPS performance and dual-channel simultaneous sampling, providing two matched acquisition channels for differential probing or trigger-and-acquire configurations. The serialized LVDS output simplifies connection to high-end FPGAs implementing deep-memory capture and real-time FFT processing. Programmable gain (3.5 dB coarse + 6 dB fine) allows the instrument's input attenuator chain to be simplified - the ADC itself can be range-adjusted to optimize SNR/SFDR for the specific input amplitude. The internal reference eliminates drift concerns for DC-accurate measurements. In a 4-channel oscilloscope the designer can pair two ADS6244 devices for 4 matched channels, or migrate to the feature-compatible quad-channel ADS644X/ADS642X families (per TI datasheet SLAS531A/SLAS532A) for higher channel counts without changing the PCB layout pattern.
Recommended
Phased-Array Radar & Beamforming Receivers
Phased-array radar, MIMO radar, and electronic-warfare receivers require multiple synchronized ADC channels with sub-sample phase coherence, exactly what the ADS6244IRGZ25's dual simultaneous-sampling architecture provides. At 105 MSPS per channel the device captures intermediate-frequency (IF) signals from each antenna element, and tiling multiple ADS6244s (e.g. 16 devices for 32 elements) builds a coherent array in a compact PCB area. The serialized LVDS interface minimizes FPGA pin consumption, allowing affordable FPGAs to interface with many synchronized channels. The 14-bit resolution delivers sufficient dynamic range for clutter rejection in radar returns, while the 3.5 dB coarse + 6 dB fine gain programmability enables each channel's input range to be matched to the specific receiver front-end. Per the TI datasheet, the part is functionally compatible with the quad-channel ADS644X/ADS642X families for higher-element-count arrays.
Recommended
Recommended Products Summary
Engineering reference data for ADS6244IRGZ25 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADS6245IRGZ25 | ADS6242IRGZR | ADS6129IRGZ25 | ADS61B29IRGZ25 |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same |
| Sample Rate (max) | 105 MSPS | 125 MSPS (+19%) | 65 MSPS (-38%) | 105 MSPS (same) | 80 MSPS (-24%) |
| Resolution | 14 bit | 14 bit (same) | 14 bit (same) | 12 bit (lower) | 12 bit (lower) |
| Number of Channels | 2 | 2 (same) | 2 (same) | 2 (same) | 2 (same) |
| Output Interface | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS |
| Supply Voltage | 3.3 V | 3.3 V (same) | 3.3 V (same) | 3.3 V (same) | 3.3 V (same) |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Approx. Unit Price (qty-1) | $42.50 | $55+ (higher speed grade) | $30 (lower speed grade) | $28 (12-bit alternative) | $35 (12-bit wideband) |
Key Differentiators
- Same-package 125 MSPS upgrade path (vs ADS6245IRGZ25)
- Pin-compatible 12-bit option for cost-sensitive channels (vs ADS6129IRGZ25)
- Dual simultaneous-sampling channels in single package (vs Single-channel ADCs (e.g. discrete ADS58C28))
Design Notes
Decouple each AVDD/AVSS and DVDD/DVSS pin pair with a 0.1 uF X7R ceramic capacitor placed within 5 mm of the pin, plus a 10 uF bulk tantalum or ceramic capacitor near the package. The ADS6244IRGZ25 is sensitive to supply noise; use a ferrite bead between the analog and digital 3.3 V rails to prevent digital switching noise from coupling into the analog front-end. A low-noise LDO (e.g. LP38690 or TPS7A4700) is recommended for the AVDD rail.
The 48-VQFN (RGZ) package has theta_JA of approximately 31.4 C/W with the exposed pad soldered to a 1 sq inch copper pour. At typical 105 MSPS dual-channel operation (~1 W dissipation), junction temperature rises ~31 C above ambient - well within the 125 C max for industrial operation. Use at least 4 thermal vias (0.3 mm drill) under the exposed pad to inner ground planes, and avoid cutting the ground pour beneath the ADC with signal traces.
Route the differential analog inputs (INP_A/INN_A, INP_B/INN_B) and clock (CLKP/CLKN) as 100 ohm differential microstrip pairs with matched lengths within 0.5 mm. Place the ADC close to the driving amplifier (THS4513 or similar) to minimize trace capacitance. Route the LVDS output pairs (D0_P/N, D1_P/N, OUTCLK_P/N) as 100 ohm differential pairs with length matching, and place the 100 ohm termination resistor at the FPGA end - never at the ADC end. Reference TI datasheet section 'PCB Layout Guidelines' for full recommendations.
At 105 MSPS the serialized LVDS data rate reaches 595 Mbps per channel; FPGA LVDS receivers must be rated 600 Mbps or higher. Use IBIS simulation to verify signal integrity across PVT corners, particularly across the LVDS-to-FPGA interface. Keep the clock jitter below 1 ps RMS to preserve SNR; the LMK04828 or LMK04826 jitter cleaner is recommended for the clock source. Enable spread-spectrum clocking only with caution - it may degrade ADC SNR.
Do not float the exposed thermal pad - it must be soldered to the ground plane for thermal dissipation. Do not operate without proper SPI configuration - default register state may not match the application. Always issue a hardware reset (SEN high-to-low transition with SDATA = 1) after power-up before capturing data. The minimum input amplitude (400 mVpp) is differential - driving a single-ended signal requires a balun or DC bias network. Verify the VCM output (1.5 V) is bypassed with 0.1 uF to AVSS if used to bias the input common-mode.
Compliance Information
RoHS compliant per TI product page. Lead-free 48-VQFN (RGZ) package supports 260C reflow per JEDEC J-STD-020. Halogen-free designation not explicitly listed in verified data - set to 'unknown'. Not AEC-Q100 qualified; for automotive applications consider AEC-Q100 qualified alternatives or contact TI.
