ATSAMA5D43A-CU - 600MHz Cortex-A5 MPU, 128KB ROM | Microchip
MPN: ATSAMA5D43A-CU ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $11.39 | $11.39 |
| 10 | $10.25 | $102.50 |
| 100 | $9.18 | $918.00 |
| 500 | $8.42 | $4,210.00 |
| 1,000 | $7.85 | $7,850.00 |
ATSAMA5D43A-CU Overview
An ARM Cortex-A5 MPU is a microprocessor unit built around the ARMv7-A architecture that runs at frequencies up to 600 MHz while integrating memory management, NEON media processing, and Java acceleration. The Cortex-A5 belongs to the application processor tier of the ARM Cortex family - above Cortex-M microcontrollers but below Cortex-A7/A9/A15/A53 in performance - and is widely deployed in industrial HMI, point-of-sale terminals, and low-power video gateways. MPU ICs sit above microcontrollers in the embedded hierarchy because they execute an operating system (typically Linux) rather than bare-metal firmware.
Key features of the ATSAMA5D43A-CU include NEON SIMD media engine for H.264 720p decode at 30 fps, hardware AES/SHA/TRNG secure boot, two high-speed USB 2.0 ports (host + device), two EMAC gigabit Ethernet MACs, and a 12-bit ADC with up to 12 channels. Power management is handled through internal voltage regulators with deep-sleep power-down mode drawing under 1 mA.
The architecture pairs the Cortex-A5 core with a multi-layer AHB/APB bus matrix, dedicated peripheral DMA controllers, and a video decoder subsystem. The 289-LFBGA package provides excellent electrical performance for high-speed DDR interfaces and exposes the full set of multimedia peripherals, including an LCD controller and an image sensor interface.
Typical applications include industrial HMI panels, smart energy gateways, point-of-sale terminals, medical patient monitors, and secure IoT edge nodes. The NEON engine and LCD controller make it well suited for graphical operator interfaces, while the hardware crypto accelerator supports secure boot and TLS/IPsec offload.
When designing with this MPU, allocate at least 4 layers for the DDR2/DDR3 routing to maintain signal integrity, and provide a 1.0 V core supply decoupled with 100 nF + 10 uF capacitors within 5 mm of each VDDCORE ball. The 289-LFBGA requires a 0.8 mm pitch land pattern and is intended for reflow soldering with MSL3 moisture sensitivity handling.
This page synthesizes distributor pricing, drop-in alternatives drawn from the SAMA5D4 family, and practical PCB design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for ATSAMA5D43A-CU — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ATSAMA5D43A-CU (same form factor and footprint) — differing in Package, USB, Operating Temperature, Ethernet, MSL Level.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ATSAMA5D44A-CU
✅ Drop-In✓ In Stock
$21.4 / Unit
View Datasheet →ATSAMA5D42A-CU
✅ Drop-In✓ In Stock
$18.24 / Unit
View Datasheet →ATSAMA5D42B-CU
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →ATSAMA5D41B-CU
✅ Drop-In✓ In Stock
$10.95 / Unit
View Datasheet →ATSAMA5D43A-CUR
✅ Drop-In✓ In Stock
$9.83 / Unit
View Datasheet →ATSAMA5D43A-CU Maximum Ratings & Electrical Characteristics
| Core Architecture | ARM Cortex-A5 (ARMv7-A) |
| Maximum Core Frequency | 600 MHz |
| Core Count | 1 |
| Data Bit Width | 32-bit |
| Instruction Cache | 32 KB |
| Data Cache | 32 KB |
| ROM | 128 KB (boot + crypto library) |
| External Memory Interface | 16-bit EBI, supports DDR2/LPDDR/DDR3, NAND Flash with ECC |
| Package | 289-LFBGA (14x14 mm, 0.8 mm pitch) |
| Mounting Type | Surface Mount |
| Supply Voltage (Core) | 1.0 V to 1.2 V |
| Supply Voltage (I/O) | 1.8 V / 3.3 V |
| Operating Temperature | -40C to +85C (industrial) |
| MSL Level | 3 (per JEDEC J-STD-020) |
| USB Ports | 2 x USB 2.0 High-Speed (host + device) |
| Ethernet MAC | 2 x GMAC (10/100/1000 Mbps) |
| Video Decode | H.264 720p @ 30 fps (NEON) |
| Hardware Crypto | AES, SHA, TRNG, secure boot |
| ADC | 12-bit, up to 12 channels |
| RoHS Status | Compliant |
ATSAMA5D43A-CU Pin Configuration
| Pin A1 | VDDANA — Analog supply |
| Pin A2 | GNDANA — Analog ground |
| Pin B1 | DDR_DQ0 — DDR data bit 0 |
| Pin B2 | DDR_DQ1 — DDR data bit 1 |
| Pin C1 | DDR_DQS — DDR data strobe |
| Pin C2 | DDR_DQM — DDR data mask |
| Pin D1 | DDR_A0 — DDR address bit 0 |
| Pin D2 | DDR_BA0 — DDR bank address 0 |
| Pin E1 | DDR_CK — DDR clock positive |
| Pin E2 | DDR_CKN — DDR clock negative |
| Pin F1 | VDDCORE — Core supply 1.0-1.2 V |
| Pin F2 | GND — Common ground |
| Pin G1 | TDI — JTAG test data in |
| Pin G2 | TCK — JTAG test clock |
| Pin H1 | TDO — JTAG test data out |
| Pin H2 | TMS — JTAG test mode select |
| Pin J1 | NRST — System reset (active low) |
| Pin J2 | JTAGSEL — JTAG selection |
Typical Applications
ATSAMA5D43A-CU is suitable for 6 applications: Industrial HMI Panel, Smart Energy Gateway, Point-of-Sale Terminal, Medical Patient Monitor, Secure IoT Edge Node, Video Intercom and Door Station.
Industrial HMI Panel
The ATSAMA5D43A-CU is well suited for industrial human-machine interface (HMI) panels because it integrates an LCD controller supporting up to 2048x2048 resolution, two gigabit Ethernet MACs for industrial networking, and the -40C to +85C industrial temperature range. The 600 MHz Cortex-A5 core paired with the NEON SIMD engine accelerates graphical frame composition and H.264 720p decode for animated operator screens. Compared to a Cortex-M7 HMI, the SAMA5D43 cuts GUI render time roughly tenfold while running a full Linux stack for OPC-UA and Modbus-TCP. Reference design: SAMA5D4 Xplained Ultra board with Linux4SAM BSP.
Recommended
Smart Energy Gateway
The ATSAMA5D43A-CU fits smart energy gateways because it provides two gigabit Ethernet MACs, hardware AES/SHA crypto for TLS/IPsec offload, and the Cortex-A5 MMU required for running a full Linux IPsec stack. The hardware TRNG plus secure boot ROM enables tamper-resistant firmware validation in grid-side and meter-side deployments. With 600 MHz CPU performance, the part can route encrypted MQTT traffic while simultaneously driving an LCD for local status display. Compared to a Cortex-M4 gateway, the SAMA5D43 adds the headroom needed for OpenWrt routing plus on-device analytics.
Recommended
Point-of-Sale Terminal
The ATSAMA5D43A-CU is appropriate for point-of-sale (POS) terminals because the NEON engine accelerates H.264 720p decode for promotional video, the LCD controller drives customer-facing displays, and the two USB 2.0 high-speed ports connect barcode scanners and payment peripherals. Hardware AES offloads PCI-PTS PIN encryption without loading the CPU. The 128 KB ROM boot code enables secure boot chains required for PCI-PTS 6.x certification. With Linux4SAM BSP support, integrators can run verified Android or embedded Linux distributions on the same hardware.
Recommended
Medical Patient Monitor
The ATSAMA5D43A-CU suits medical patient monitors because the 600 MHz Cortex-A5 core provides enough processing headroom for ECG/SpO2 waveform DSP while the LCD controller drives the bedside display. The two EMAC ports enable isolated network connectivity plus an Ethernet-based medical device bus. Hardware AES and secure boot support FDA cybersecurity guidance by enabling encrypted firmware updates. The -40C to +85C industrial temperature range plus MTBF data from Microchip's longevity program make it viable for IEC 60601-1 certified designs.
Recommended
Secure IoT Edge Node
The ATSAMA5D43A-CU is a strong fit for secure IoT edge nodes because the 128 KB ROM contains the secure-boot ROM monitor and hardware AES/SHA accelerators that offload TLS 1.3 handshake compute. The TRNG provides high-entropy key material for per-device identity. The two gigabit Ethernet MACs let the node act as a router/gateway plus an edge-compute device on the same board. Compared to Cortex-M7 IoT nodes, the SAMA5D43 supports full containers (Docker via Linux4SAM) for over-the-air model deployment at the edge.
Recommended
Video Intercom and Door Station
The ATSAMA5D43A-CU is ideal for IP video intercom and door-station designs because the NEON-accelerated H.264 720p30 engine streams video over Ethernet while the LCD controller drives the indoor panel display. Hardware AES offloads TLS encryption on the streaming channel. The two USB ports support a camera sensor plus a touchscreen controller. The deep-sleep power-down mode drawing under 1 mA enables standby power budgets compatible with PoE class 1 devices. Reference Linux4SAM builds include an intercom demo with ONVIF profile S support.
Recommended
Recommended Products Summary
Engineering reference data for ATSAMA5D43A-CU — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ATSAMA5D44A-CU | ATSAMA5D42A-CU | ATSAMA5D42B-CU | ATSAMA5D41B-CU |
|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 289-LFBGA (14x14) | 289-LFBGA (14x14) - same | 289-LFBGA (14x14) - same | 289-LFBGA (14x14) - same | 289-LFBGA (14x14) - same |
| Core Architecture | ARM Cortex-A5 600 MHz | ARM Cortex-A5 600 MHz | ARM Cortex-A5 600 MHz | ARM Cortex-A5 600 MHz | ARM Cortex-A5 600 MHz |
| On-chip SRAM | 0 KB (128 KB ROM) | 128 KB SRAM + 128 KB ROM | 0 KB (128 KB ROM) | 0 KB (128 KB ROM) | 0 KB (128 KB ROM) |
| External Memory Interface | 16-bit DDR2/LPDDR/DDR3 | 16-bit DDR2/LPDDR/DDR3 | 16-bit DDR2/LPDDR/DDR3 | 16-bit DDR2/LPDDR/DDR3 | 16-bit DDR2/LPDDR/DDR3 |
| USB Ports | 2 x USB 2.0 HS | 2 x USB 2.0 HS | 2 x USB 2.0 HS | 2 x USB 2.0 HS | 1 x USB 2.0 HS |
| Gigabit Ethernet MACs | 2 x GMAC | 2 x GMAC | 2 x GMAC | 2 x GMAC | 1 x GMAC |
| Hardware Crypto | AES, SHA, TRNG | AES, SHA, TRNG | AES, SHA, TRNG | AES, SHA, TRNG | AES, SHA, TRNG |
| Video Decode (NEON) | H.264 720p30 | H.264 720p30 | H.264 720p30 | H.264 720p30 | H.264 720p30 |
Key Differentiators
- Balanced 600 MHz Cortex-A5 with on-chip security ROM (vs ATSAMA5D27A-CU)
- Two gigabit Ethernet MACs versus one on lower-cost variants (vs ATSAMA5D41B-CU)
- Two USB 2.0 HS ports versus one on reduced variants (vs ATSAMA5D41B-CU)
Design Notes
Estimated: at 600 MHz full-clock and 1.2 V core supply, the ATSAMA5D43A-CU draws approximately 0.4 A core current plus DDR controller and peripheral current. Total power dissipation is roughly 1.5 W under typical workload. The 289-LFBGA package requires thermal vias under the center balls to a 4-layer inner ground plane; without vias, junction temperature can exceed 105 C. Place at least a 50 mm x 50 mm copper pour on the top layer connected to GND balls.
The 16-bit DDR2/DDR3 interface must be routed as a matched-length group. Estimated: keep DDR data/strobe traces within +/-25 mil length match and within +/-50 mil of the clock pair. Use 100 ohm differential impedance for DDR clock and 50 ohm single-ended for data/address. The SAMA5D4 hardware design guide recommends four PCB layers minimum (signal/GND/power/signal) with the inner GND plane unbroken beneath the DDR routing.
Decouple each VDDCORE ball with a 100 nF X7R ceramic capacitor placed within 5 mm of the ball, plus a single 10 uF bulk capacitor per four VDDCORE balls. The VDDIOP and VDDIOM supplies also require 100 nF decoupling. The PMIC companion should be a MIC2800 or similar with sequencing to bring VDDCORE up before VDDIOP. Inrush current on cold-start is roughly 600 mA; size the upstream LDO accordingly.
Do not confuse ATSAMA5D43A-CU with ATSAMA5D43B-CU - the B suffix denotes a silicon revision update. The package pinout is identical but errata fixes differ. Also avoid mixing SAMA5D4 with SAMA5D2 packages: although both are 289-ball BGA, the ball map is different and cross-mounting will short power rails. The boot configuration pins BMS (boot mode select) and JTAGSEL must be pulled to the correct state at NRST release or the part will fail to boot.
Place the boot SPI flash and the boot NAND flash on the same memory bus segment to allow alternate boot sources. The image sensor interface and LCD controller data lanes should be routed on inner layers with length matching per the SAMA5D4 layout checklist. Keep the USB 2.0 differential pairs at 90 ohm differential impedance and length-matched to within 150 mil. The two gigabit Ethernet MII/RGMII signals to the PHY require source-synchronous length matching; route on the top layer over a continuous GND plane.
Compliance Information
RoHS and REACH compliant per Microchip product declaration. Not AEC-Q100 qualified - this is an industrial/consumer MPU, not an automotive grade part. Lead-free reflow soldering compatible per JEDEC J-STD-020 MSL3.