CD74HC138 - 3-to-8 Line Decoder/Demux 2-6V | Texas Instruments
料号： CD74HC138 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $0.55 | $0.55 |
| 10 | $0.45 | $4.50 |
| 100 | $0.32 | $32.00 |
| 500 | $0.26 | $130.00 |
| 1,000 | $0.21 | $210.00 |
| 3,000 | $0.18 | $540.00 |
CD74HC138 概述
A decoder/demultiplexer is a combinational logic device in the broader logic IC family (logic -> decoder -> demultiplexer -> data routing IC). Decoders convert binary-coded inputs into one-hot outputs, while the same circuit used with enables asserted acts as a demultiplexer routing data to one of eight output lines. The CD74HC138 belongs to TI's High Speed CMOS (HC) logic family, offering CMOS low power with LSTTL-comparable speed.
Key features include three binary select inputs (A0, A1, A2) with full on-chip decoding, three enable inputs (two active-low, one active-high) supporting cascaded 4-to-16 or larger decoders without external gates, eight active-low outputs suited to memory chip-select (CS) and enable lines, low quiescent CMOS power consumption, and wide 2V to 6V supply operation typical of the HC family.
Architecturally, the CD74HC138 uses high-speed silicon-gate CMOS construction with speeds comparable to low-power Schottky TTL logic. When used as a demultiplexer, the active-low enables serve as the data input while the select inputs route the data to the addressed output, eliminating external inverter gates.
Typical applications include memory address decoding for SRAM/EPROM/Flash chip selects, I/O port expansion in microprocessor systems, data routing and demultiplexing, and address latching in embedded control systems. Its inverting outputs directly drive active-low memory CS/CE inputs without external inverters.
Design tip: tie unused enable inputs to their inactive levels and keep select lines short; for 4-to-16 decoding, cascade two devices using one enable as the MSB select. Verify AC timing at your supply voltage and load.
This page synthesizes distributor pricing, drop-in alternatives, cross-reference data, and practical design notes not found in the manufacturer datasheet.
直接替换替代料： CD74HC138 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： CD74HC138 （相同外形与封装尺寸） ——差异在于 Enable Inputs, Logic Family, Mounting Type, Package, Select Inputs.
快速对比工具——选择替代料号进行并排对比：
SN74HC138
✅ 直接替换📋 参考替代料（不在目录中）
CD74HCT138
✅ 直接替换📋 参考替代料（不在目录中）
CD74HC138-Q1
✅ 直接替换📋 参考替代料（不在目录中）
CD74HC238
✅ 直接替换📋 参考替代料（不在目录中）
MC74HC138ANG
✅ 直接替换📋 参考替代料（不在目录中）
MC74HC138AFG
✅ 直接替换📋 参考替代料（不在目录中）
74HC138D
✅ 直接替换📋 参考替代料（不在目录中）
CD74HC138 最大额定值与电气特性
| Logic Function | 3-to-8 Line Decoder/Demultiplexer, inverting outputs |
| Logic Family | HC (High Speed CMOS) |
| Supply Voltage Range | 2 V to 6 V |
| Select Inputs | 3 (A0, A1, A2) |
| Outputs | 8 active-low (Y0-Y7) |
| Enable Inputs | 3 (two active-low, one active-high) |
| 输出类型 | Inverting (active-low) |
| Technology | High-speed silicon-gate CMOS |
| Input Logic Compatibility | CMOS (HC level) |
| 封装 | 16-pin PDIP / SOIC (per ordering suffix) |
| 安装类型 | Through-Hole (PDIP variant) / Surface Mount (SOIC variant) |
| RoHS 状态 | Compliant |
| Datasheet Document | SCHS147J (November 1998 - Revised November 2021) |
| Typical Use | Memory address decoding, data routing |
CD74HC138 引脚配置
| 引脚 1 | A0 — Select input 0 (LSB) |
| 引脚 2 | A1 — Select input 1 |
| 引脚 3 | A2 — Select input 2 (MSB) |
| 引脚 4 | E1 — Enable input, active-low |
| 引脚 5 | E2 — Enable input, active-low |
| 引脚 6 | E3 — Enable input, active-high |
| 引脚 7 | O7 — Output 7, active-low (O7 bar) |
| 引脚 8 | GND — Ground |
| 引脚 9 | O6 — Output 6, active-low (O6 bar) |
| 引脚 10 | O5 — Output 5, active-low (O5 bar) |
| 引脚 11 | O4 — Output 4, active-low (O4 bar) |
| 引脚 12 | O3 — Output 3, active-low (O3 bar) |
| 引脚 13 | O2 — Output 2, active-low (O2 bar) |
| 引脚 14 | O1 — Output 1, active-low (O1 bar) |
| 引脚 15 | O0 — Output 0, active-low (O0 bar) |
| 引脚 16 | VCC — Supply voltage, 2 V to 6 V |
典型应用
CD74HC138 适用于 6 应用s: Memory Address Decoding, I/O Port Expansion in Microprocessor Systems, 4-to-16 Cascaded Decoding, LED and Indicator Multiplexing, Automotive Body and Module Control, Data Routing and Demultiplexing.
Memory Address Decoding
The CD74HC138's primary application is memory address decoding for SRAM, EPROM, and Flash chip-select lines. Its eight active-low outputs directly drive active-low CS and CE memory pins without external inverter gates, saving board space and propagation delay in the critical address-to-select path. Three select inputs (A0-A2) decode high address bits into one of eight chip-select strobes, while the three enables (two active-low, one active-high) can qualify the decode with a bus or memory-region signal. With HC-family CMOS speed comparable to low-power Schottky TTL per the TI datasheet SCHS147J, the device keeps address-setup timing margins healthy in embedded systems running at 5V or 3.3V, and its CMOS quiescent current keeps standby power low in battery-backed memory subsystems.
推荐
I/O Port Expansion in Microprocessor Systems
In microprocessor and microcontroller systems, the CD74HC138 expands a few address lines into eight peripheral-select strobes, letting one 3-bit port address up to eight devices such as UARTs, timers, and port expanders. The active-low outputs suit peripheral CS inputs directly, and the enable inputs allow a read/write or address-valid signal to gate the strobe so devices only see a select pulse when the bus transaction is valid. Operating from 2V to 6V, the decoder works with both 5V legacy MCUs and 3.3V systems. Designers should verify propagation delay against peripheral setup requirements and tie unused enables to their inactive levels to prevent spurious selects, per TI datasheet SCHS147J guidance for data routing applications.
推荐
4-to-16 Cascaded Decoding
Two CD74HC138 devices cascade into a 4-to-16 decoder with zero external gates: the MSB (A3) drives the active-high enable of the lower device and, through its polarity, an active-low enable of the upper device, so exactly one of the sixteen outputs asserts at any time. This is a textbook technique described in the TI datasheet SCHS147J and is widely used when memory maps or I/O spaces exceed eight regions. The approach preserves the CMOS low power of the HC family while doubling decode capacity, and it can be extended further by using additional enables as higher-order selects. Ensure all select lines switch monotonically to avoid decode glitches during address transitions, and consider Schmitt-trigger buffers on slow address lines.
推荐
LED and Indicator Multiplexing
The CD74HC138 is used to time-multiplex LED banks, segment displays, and indicator arrays by driving one row or digit at a time through its decoded outputs. The inverting (active-low) outputs match common-anode LED row drivers or the enable inputs of row-driver transistors directly. Because the decoder asserts exactly one output per select code, scanning logic only needs a 3-bit counter on A0-A2, and the enable inputs provide a blanking function - deasserting the enables turns all rows off instantly, which prevents ghosting between scan steps. At 5V the HC outputs source and sink enough current to drive transistor base resistors, though series resistors or driver transistors are recommended for the LED load itself, since HC outputs are specified for logic drive rather than high LED current.
推荐
Automotive Body and Module Control
For automotive modules that need multiple low-side select strobes - relay banks, lamp circuits, sensor enables - the CD74HC138-Q1 variant provides the same 3-to-8 decode function with AEC-Q100 qualification and extended temperature capability. A microcontroller's 3 GPIO pins become eight qualified select lines, reducing pin count and wiring harness complexity. The active-low outputs suit the enable inputs of high-side drivers and automotive power switches, and the enable inputs allow a master-fault or ignition signal to gate all strobes off simultaneously for safe-state control. Because the entire function is pure combinational CMOS logic with no software dependency, the decoder provides deterministic, glitch-free select behavior valued in safety-related body electronics, according to TI's CD74HC138-Q1 product documentation.
推荐
Data Routing and Demultiplexing
Used as a demultiplexer, the CD74HC138 routes a single data stream to one of eight destinations: the data input drives an active-low enable while A0-A2 select the destination output, whose value becomes the inverse of the data when asserted. This topology is described in the TI datasheet SCHS147J and suits clock distribution, one-wire bus fan-out, and control-line routing in industrial and test systems. The HC family's 2V to 6V range lets the same routing block serve both 5V and 3.3V signal domains. Designers should account for the output inversion (add an inverter on the data line or invert the data logically), and for duty-cycle distortion at low supply voltages where HC propagation delays increase relative to the 5V characterization data.
推荐
推荐产品汇总
工程参考数据： CD74HC138 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | SN74HC138 | CD74HCT138 | CD74HC138-Q1 | MC74HC138ANG | 74HC138D |
|---|---|---|---|---|---|---|
| Package | 16-pin PDIP/SOIC | 16-pin PDIP/SOIC/TSSOP - same footprint per suffix | 16-pin PDIP/SOIC - same | 16-pin - same | PDIP-16 - same | SOIC-16 - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | onsemi | Nexperia |
| Logic Function | 3-to-8 decoder, inverting outputs | 3-to-8 decoder, inverting | 3-to-8 decoder, inverting | 3-to-8 decoder, inverting | 3-to-8 decoder, inverting | 3-to-8 decoder, inverting |
| Supply Voltage | 2 V to 6 V | 2 V to 6 V | 4.5 V to 5.5 V (TTL) | 2 V to 6 V | 2 V to 6 V | 2 V to 6 V |
| Input Thresholds | CMOS level (HC) | CMOS level (HC) | TTL-compatible | CMOS level (HC) | CMOS level (HC) | CMOS level (HC) |
| Automotive Grade | No | No | No | Yes (AEC-Q100) | No | No |
| Output Polarity | Active-low | Active-low | Active-low | Active-low | Active-low | Active-low |
关键差异点
- Three enables enable glueless cascading （对比 Simple 2-input-select decoders)
- TTL-input option in same footprint （对比 CD74HCT138)
- Active-low outputs match memory CS pins （对比 CD74HC238)
设计说明
Tie all three enable inputs to their correct inactive levels: E1 and E2 must be pulled high and E3 pulled low (or driven deliberately) if unused. A floating CMOS enable can cause oscillation, increased ICC, or spurious output asserts because HC inputs must never be left floating. For 4-to-16 decoding, cascade two devices with the MSB on the enables rather than gating outputs externally, which adds delay.
During address transitions, two select codes can briefly be active simultaneously (decode glitches) because HC select inputs do not switch simultaneously. In memory chip-select applications, gate the decoder outputs with an address-valid or strobe signal via the enable inputs so that selects only pulse when the bus address is stable. Add 0.1uF decoupling close to the VCC pin; HC CMOS speed degrades at low VCC, so re-verify timing at 3.3V.
Estimated: HC-family CMOS quiescent current is microamps at room temperature, so static dissipation is negligible; dynamic dissipation dominates and scales as C x V x f per switching input/output. For a 74HC138 driving eight outputs at 5V and 1 MHz with 15 pF loads, estimated dynamic power is on the order of a few milliwatts. Avoid inputs floating and avoid signals exceeding VCC + 0.5V to prevent CMOS latch-up or excess current.
合规信息
RoHS compliant per TI product page for current production suffixes; the AEC-Q100 qualified variant is the separate CD74HC138-Q1. Other compliance attributes should be confirmed on the TI quality summary page per ordering suffix.
