DSPIC33FJ128GP802-I/SP - 16-bit DSC 40MIPS 128KB | Microchip
MPN: DSPIC33FJ128GP802-I/SP ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.2 | $7.20 |
| 10 | $6.55 | $65.50 |
| 100 | $5.9 | $590.00 |
| 500 | $5.4 | $2,700.00 |
| 1,000 | $4.95 | $4,950.00 |
DSPIC33FJ128GP802-I/SP Overview
A Digital Signal Controller combines the computational core of a digital signal processor (DSP engine with a 17-bit x 17-bit single-cycle hardware multiplier, barrel shifter, and 40-bit accumulators) with the peripheral set of a microcontroller. In the power-management hierarchy, the dsPIC33F family sits between general-purpose 16-bit MCUs such as the PIC24H and dedicated DSPs, offering deterministic control plus signal processing in one silicon device.
Key features include 8-channel DMA for data-intensive peripherals, a 12-bit ADC with up to 500 ksps throughput, two UARTs, two SPI and I2C ports, and an output-compare/PWM module suited to motor control and digital power conversion. The GP (general purpose) variant emphasizes communications and analog acquisition, while the pin-compatible MC variant targets motor control.
Technically, the dsPIC33F core executes most instructions in a single cycle from zero-wait-state Flash at 3.0V to 3.6V operation, and supports an internal fast RC oscillator, phase-locked loop clocking, and in-circuit serial programming (ICSP) via the MCLR/PGD/PGC pins for field upgrades without removing the device.
Typical applications include digital power supplies and LED drivers, sensor conditioning and data loggers, and industrial control panels where through-hole DIP packaging eases prototyping and repair.
Design consideration: all analog inputs share port B pins - route the AVDD/AVSS analog supply pair on a quiet ground island to preserve ADC accuracy.
This page synthesizes distributor pricing, drop-in alternatives within the same 28-SPDIP footprint, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for DSPIC33FJ128GP802-I/SP — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33FJ128GP802-I/SP (same form factor and footprint) — differing in Package, Core Architecture, Operating Temperature, Timers, ADC Resolution.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33FJ128GP802-E/SP
✅ Drop-In✓ In Stock
$4.38 / Unit
View Datasheet →DSPIC33FJ128GP202-I/SP
✅ Drop-In✓ In Stock
$3.42 / Unit
View Datasheet →DSPIC33EP64MC202-I/SP
✅ Drop-In✓ In Stock
$3.1 / Unit
View Datasheet →DSPIC33EV32GM002-E/SP
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33FJ06GS202-I/SP
✅ Drop-In✓ In Stock
$3.52 / Unit
View Datasheet →DSPIC33FJ06GS202A-E/SP
✅ Drop-In✓ In Stock
$1 / Unit
View Datasheet →DSPIC33FJ128GP802-I/SP Maximum Ratings & Electrical Characteristics
| Core Architecture | 16-bit dsPIC33F DSC |
| Maximum CPU Speed | 40 MIPS (40 MHz) |
| Program Memory (Flash) | 128 KB |
| SRAM | 16 KB |
| DMA Channels | 8 |
| Operating Voltage | 3.0 V to 3.6 V |
| ADC Resolution | 12-bit |
| ADC Throughput | up to 500 ksps |
| Timers | 5 x 16-bit |
| UART | 2 |
| SPI | 2 |
| I2C | 2 |
| Input Capture / Output Compare | 4 / 4 |
| Operating Temperature | -40C to +85C (I grade) |
| Package | 28-pin SPDIP (0.300 in, 7.62 mm) |
| Mounting Type | Through Hole |
| Programming Interface | ICSP (2-wire, PGD/PGC) |
DSPIC33FJ128GP802-I/SP Pin Configuration
| Pin 1 | MCLR — Master clear reset / programming voltage input |
| Pin 2 | AN0/VREF+/CN2/RB0 — Analog input 0 / ADC positive reference / port B0 |
| Pin 3 | AN1/VREF-/CN3/RB1 — Analog input 1 / ADC negative reference / port B1 |
| Pin 4 | AN2/SS1/CN4/RB2 — Analog input 2 / SPI1 slave select / port B2 |
| Pin 5 | AN3/INDX/CN5/RB3 — Analog input 3 / QEI index / port B3 |
| Pin 6 | AN4/QEA/IC7/CN6/RB4 — Analog input 4 / QEI phase A / input capture 7 / port B4 |
| Pin 7 | VDD — Positive supply (3.0 V to 3.6 V) |
| Pin 8 | VSS — Ground reference |
| Pin 9 | OSC1/CLKI/CN12/RC12 — Oscillator crystal input / external clock input |
| Pin 10 | OSC2/CLKO/RC15 — Oscillator crystal output / clock output |
| Pin 11 | RP0/U1TX/SDO1 — Remappable pin: UART1 TX / SPI1 data out |
| Pin 12 | RP1/U1RX/SDI1 — Remappable pin: UART1 RX / SPI1 data in |
| Pin 13 | VSS — Ground reference |
| Pin 14 | VDD — Positive supply (3.0 V to 3.6 V) |
| Pin 15 | RP2/SCL1 — Remappable pin: I2C1 clock |
| Pin 16 | RP3/SDA1 — Remappable pin: I2C1 data |
| Pin 17 | AN5/QEB/IC8/CN7/RB5 — Analog input 5 / QEI phase B / input capture 8 / port B5 |
| Pin 18 | RP13/U2RX — Remappable pin: UART2 RX |
| Pin 19 | RP14/U2TX — Remappable pin: UART2 TX |
| Pin 20 | VCAP/VDDCORE — CPU core voltage - connect low-ESR capacitor to VSS |
| Pin 21 | RP5/U1RTS — Remappable pin: UART1 RTS / general remappable I/O |
| Pin 22 | RP6/U1CTS — Remappable pin: UART1 CTS / general remappable I/O |
| Pin 23 | RP7/SCL2 — Remappable pin: I2C2 clock |
| Pin 24 | RP8/SDA2 — Remappable pin: I2C2 data |
| Pin 25 | RP9/SDO2 — Remappable pin: SPI2 data out |
| Pin 26 | RP10/SDI2/SOSCI/RC13 — Remappable pin: SPI2 data in / secondary oscillator input |
| Pin 27 | AVDD — Analog supply for ADC (connect to VDD with filtering) |
| Pin 28 | AVSS — Analog ground for ADC |
Typical Applications
DSPIC33FJ128GP802-I/SP is suitable for 6 applications: Digital Power Conversion, Sensor Conditioning and Data Loggers, Industrial Control Panels, Motor Control (Auxiliary / Communications), Audio Signal Processing, Prototyping and Education.
Digital Power Conversion
The DSPIC33FJ128GP802-I/SP fits switch-mode power supply and LED-driver control because its 40 MIPS DSP core executes proportional-integral control loops with single-cycle 16x16 MAC instructions, while the 12-bit ADC samples up to 500 ksps for current- and voltage-loop feedback. ADC scan mode triggered from an output-compare PWM event gives deterministic sampling instants, and 8 DMA channels move results to RAM without CPU intervention, cutting loop latency. Typical use places the DSC between the feedback divider and the PWM gate driver stage; the trade-off is that the 40 MHz maximum clock bounds achievable switching frequencies compared with dedicated digital-power GS-series parts, which offer comparator-based instant PWM trips.
Recommended
Sensor Conditioning and Data Loggers
In data-logging and sensor-front-end designs, the GP802 combines a 12-bit, up-to-500-ksps ADC with two UARTs, two SPI buses, and two I2C ports, letting one 28-pin device talk to sensors, external memory, and a host simultaneously. The 16 KB SRAM buffers sampled waveforms, while 8 DMA channels stream ADC data so the CPU can run filtering (FIR/IIR using the DSP MAC unit) in parallel. The 128 KB Flash holds both application code and lookup/calibration tables with room for logged constants. The through-hole SPDIP package suits bench prototypes and repairable industrial loggers; for battery operation, note the ~typical mA-class active current at 40 MIPS and use idle/doze modes between samples.
Recommended
Industrial Control Panels
The 28-pin SPDIP through-hole package makes the DSPIC33FJ128GP802-I/SP a natural fit for industrial control panels and legacy-style boards where hand repair and socketed replacement matter. The -40C to +85C industrial grade covers cabinet environments, 5V-tolerant-tolerant design practice is not applicable (3.0-3.6V rails), but I/O drive and internal weak pull-ups interface readily with optocoupler and relay-driver circuitry. Two UARTs support Modbus RTU plus a service port; SPI and I2C connect displays and EEPROM. For new high-reliability designs needing wider ambient range, choose the DSPIC33FJ128GP802-E/SP grade on the identical footprint - zero PCB changes are required to upgrade.
Recommended
Motor Control (Auxiliary / Communications)
Although the GP variant targets general-purpose designs, the DSPIC33FJ128GP802-I/SP still supports basic motor control: its output-compare modules generate PWM, the 12-bit ADC reads current shunts, and the DSP engine runs Clarke/Park transforms at 40 MIPS. However, for three-phase FOC drives the pin-compatible MC802 variant and the newer DSPIC33EP64MC202-I/SP provide motor-control-tuned PWM and fault inputs, so use the GP802 where motor control is secondary to communications - for example, a conveyor controller that runs one DC motor while handling Modbus and HMI interfaces. The shared 28-SPDIP pinout means a GP802 board can migrate to an MC or EP part with firmware changes only.
Recommended
Audio Signal Processing
The dsPIC33F DSP engine - single-cycle 17x17 multiplier, dual 40-bit accumulators, and modulo/bit-reversed addressing - processes audio band filters and effects efficiently at 40 MIPS, and the 128 KB Flash retains multiple effect presets. The 12-bit ADC digitizes line-level inputs at up to 500 ksps, adequate for voice-band and utility-audio processing (intercoms, PA announcements, tone control), though hi-fi applications should add an external audio codec over the SPI port since internal 12-bit conversion limits dynamic range. Two UARTs and I2C handle remote control. The DIP package is popular in hobby and educational DSP audio platforms where experimenters socket and swap the controller.
Recommended
Prototyping and Education
The 0.300-inch 28-pin SPDIP package of the DSPIC33FJ128GP802-I/SP is the format of choice for breadboards, universal perforated boards, and university embedded-systems labs: it sockets into standard DIP-28 carriers, tolerates repeated re-insertion, and programs via a 3-wire ICSP header using PICkit-class tools under MPLAB X. The Explorer 16/32 Development Board from Microchip supports the dsPIC33 family through Plug-In Modules, providing an official low-cost path from classroom to custom PCB. Because Microchip keeps the dsPIC33FJ family active and the same die ships in SOIC/SSOP/QFN for production, students can prototype in DIP and migrate to surface mount without rewriting code.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33FJ128GP802-I/SP — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33FJ128GP802-E/SP | DSPIC33FJ128GP202-I/SP | DSPIC33EP64MC202-I/SP | DSPIC33EV32GM002-E/SP | DSPIC33FJ06GS202-I/SP |
|---|---|---|---|---|---|---|
| Package | 28-pin SPDIP | 28-pin SPDIP - same | 28-pin SPDIP - same | 28-pin SPDIP - same | 28-pin SPDIP - same | 28-pin SPDIP - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| CPU Speed | 40 MIPS | 40 MIPS | 40 MIPS | 60 MIPS | 70 MIPS | 40 MIPS |
| Program Flash | 128 KB | 128 KB | 64 KB | 64 KB | 32 KB | 6 KB |
| SRAM | 16 KB | 16 KB | 8 KB | 8 KB | 2 KB | 1 KB |
| Operating Temperature | -40C to +85C | -40C to +125C | -40C to +85C | -40C to +85C | -40C to +125C | -40C to +85C |
| Peripheral Emphasis | General purpose + comms | General purpose + comms | General purpose + comms | Motor control | Automotive/EV general purpose | Digital power (SMPS) |
Key Differentiators
- Largest Flash in the 28-pin DIP family (vs DSPIC33FJ128GP202-I/SP)
- Extended temperature option on same die (vs DSPIC33FJ128GP802-E/SP)
- 8 DMA channels reduce CPU loading (vs DSPIC33EP64MC202-I/SP)
Design Notes
The on-chip core regulator requires a low-ESR ceramic capacitor (10 uF + 0.1 uF) on VCAP/VDDCORE (pin 20), placed within 2-3 mm of the pin with a short, wide return to VSS. Never tie VCAP to VDD or drive it externally. Decouple both VDD pins (7, 14) with 100 nF ceramics, and filter AVDD (pin 27) from VDD through a ferrite bead plus 1 uF to keep ADC noise low. Estimated: active core current at 40 MIPS is tens of mA, so a 3.3V regulator rated 250 mA gives comfortable margin.
Even in through-hole designs, keep the crystal loop tight: OSC1/OSC2 (pins 9/10) with load capacitors should form the shortest possible loop to VSS. Route PGD/PGC ICSP traces with 100-ohm series resistors if shared with application I/O. Keep analog inputs (RB0-RB5) away from the crystal and PWM traces; a small ground island under AVSS/AVDD preserves 12-bit ADC accuracy. For breadboard prototyping, add 100 nF directly at each VDD pin - long DIP socket leads add inductance that degrades supply integrity.
Do not exceed 3.6 V on any VDD pin - dsPIC33F I/O is NOT 5V tolerant, so level-shift any 5V peripherals. MCLR (pin 1) must be pulled up (10 kOhm) and never driven above VDD during normal operation; ICSP applies about 8-9 V programming voltage here, so avoid heavy capacitance on this node. Remappable peripheral pins (RPx) default as inputs after reset - configure PPS registers before relying on UART/SPI signals, or firmware will appear dead on a scope.
Compliance Information
Microchip standard product is RoHS-compliant and lead-free; per-part REACH/halogen declarations should be confirmed from the Microchip product page environmental data.
