DSPIC33FJ128MC802-I/SP - 16-bit DSC, 128KB Flash, 40 MIPS | Microchip
MPN: DSPIC33FJ128MC802-I/SP ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.5 | $7.50 |
| 10 | $6.95 | $69.50 |
| 100 | $6.2 | $620.00 |
| 500 | $5.55 | $2,775.00 |
| 1,000 | $5.1 | $5,100.00 |
DSPIC33FJ128MC802-I/SP Overview
A Digital Signal Controller (DSC) is a hybrid microcontroller/DSP architecture that pairs a deterministic MCU pipeline with a single-cycle MAC DSP engine. In the broader taxonomy it sits between MCU (microcontroller) and DSP (digital signal processor) and is classified as a power-management and control IC for motor drive and digital power conversion. The dsPIC33FJ family extends PIC24 instruction-set compatibility while adding hardware multiply-accumulate, dual operand fetches, and zero-overhead looping, enabling field-oriented motor control (FOC) and digital PFC loops at modest clock rates.
Key features include 128 KB self-programmable Flash with endurance >10 k cycles, 16 KB SRAM, hardware multiply-divide, four 16-bit timer/counters, an 8-channel motor-control PWM with up to 7 complementary outputs and 8.5 ns PWM resolution, a 10-bit A/D converter at 1.1 Msps with up to 6 S/H channels, and configurable logic cells. Five 16-bit capture inputs and four PWM Fault inputs support robust industrial control loops.
The architecture uses a 16-bit modified Harvard bus with separate program and data paths, a DSP engine with dual 40-bit accumulators, and a barrel shifter. Peripheral pin select remaps digital functions across most I/O, simplifying PCB layout when motor-control and communication signals must coexist. Five VDD/VSS pairs and 5 V-tolerant I/O ease mixed-voltage interfacing.
Typical applications include BLDC/PMSM sensorless and sensored motor drives (FOC), industrial inverters and servo amplifiers, solar micro-inverters and digital PFC stages, switched-mode power supplies with adaptive loop control, and automotive body/sensor ECUs. The wide temperature grade (-40C to +85C industrial) also supports outdoor HVAC and pump controllers.
When designing with this part, keep traces between the PWM outputs and gate drivers short and isolated from the analog AVSS/AVDD pair. Use the on-chip op amps and DAC to implement current sensing rather than external analog chains when possible. Decouple each VDD pin individually and tie the exposed thermal pad (where present) to a continuous ground plane.
This page consolidates distributor pricing, drop-in same-package alternatives within the dsPIC33F family, and PCB-layout design notes not found in the manufacturer datasheet, giving embedded engineers a single source for part selection, second-source risk analysis, and BOM optimization.
Drop-in alternatives for DSPIC33FJ128MC802-I/SP — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33FJ128MC802-I/SP (same form factor and footprint) — differing in ADC, Core Architecture, Operating Temperature, Package, RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33FJ128MC802-I/MM
✅ Drop-In✓ In Stock
$4.9 / Unit
View Datasheet →DSPIC33FJ128MC802-E/SP
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33FJ64MC802-I/SP
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33FJ32MC302-I/SP
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33FJ128MC202-I/SP
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →DSPIC33FJ128MC802-I/SP Maximum Ratings & Electrical Characteristics
| Core Architecture | dsPIC33F DSC (16-bit DSP + MCU) |
| Instruction Throughput | 40 MIPS |
| Program Flash | 128 KB |
| SRAM | 16 KB |
| Supply Voltage | 3.0 V to 3.6 V |
| I/O Pins | 21 |
| Motor-Control PWM Channels | 8 (up to 7 complementary pairs) |
| PWM Resolution | 8.5 ns |
| ADC | 10-bit, up to 1.1 Msps, 6 S/H |
| Timers | 4 x 16-bit |
| Capture Inputs | 5 x 16-bit |
| PWM Fault Inputs | 4 |
| Operating Temperature | -40C to +85C (Industrial) |
| Package | 28-pin SPDIP (Skinny Plastic DIP) |
| RoHS Status | Compliant (Pb-free SPDIP) |
DSPIC33FJ128MC802-I/SP Pin Configuration
| Pin 1 | MCLR — Master Clear (reset) input, active-low |
| Pin 2 | RA0/VREF+/AN0 — Analog input 0 / VREF+ |
| Pin 3 | RA1/VREF-/AN1 — Analog input 1 / VREF- |
| Pin 4 | RA2/AN2 — Analog input 2 |
| Pin 5 | RA3/AN3 — Analog input 3 |
| Pin 6 | RA4/AN4 — Analog input 4 |
| Pin 7 | AVDD — Analog supply voltage |
| Pin 8 | AVSS — Analog ground |
| Pin 9 | OSC1/RC12 — Crystal oscillator input or GPIO |
| Pin 10 | OSC2/RC13 — Crystal oscillator output or GPIO |
| Pin 11 | RC15 — Digital I/O |
| Pin 12 | RB0/AN5 — Digital I/O / analog input 5 |
| Pin 13 | RB1/AN6 — Digital I/O / analog input 6 |
| Pin 14 | RB2/AN7 — Digital I/O / analog input 7 |
| Pin 15 | RB3/AN8 — Digital I/O / analog input 8 |
| Pin 16 | RB4/AN9 — Digital I/O / analog input 9 |
| Pin 17 | RB5/AN10 — Digital I/O / analog input 10 |
| Pin 18 | RB6/AN11/PGC1 — Digital I/O / ICSP clock |
| Pin 19 | RB7/AN12/PGD1 — Digital I/O / ICSP data |
| Pin 20 | VDD — Digital supply voltage |
| Pin 21 | VSS — Digital ground |
| Pin 22 | RC14 — Digital I/O |
| Pin 23 | PWM1H — PWM channel 1 high-side output |
| Pin 24 | PWM1L — PWM channel 1 low-side output |
| Pin 25 | PWM2H — PWM channel 2 high-side output |
| Pin 26 | PWM2L — PWM channel 2 low-side output |
| Pin 27 | PWM3H — PWM channel 3 high-side output |
| Pin 28 | VDD — Digital supply voltage |
Typical Applications
DSPIC33FJ128MC802-I/SP is suitable for 6 applications: BLDC/PMSM FOC Motor Drive, Solar Micro-Inverter / Digital PFC, Industrial Servo and Stepper Drive, Switched-Mode Power Supply (SMPS) Control, Automotive Body/Sensor ECU, HVAC Compressor and Pump Controller.
BLDC/PMSM FOC Motor Drive
The DSPIC33FJ128MC802-I/SP fits BLDC and PMSM sensorless or sensored field-oriented control drives because of its 8-channel motor-control PWM with 8.5 ns resolution, 10-bit 1.1 Msps ADC with 6 sample-and-hold channels, and dual 40-bit DSP accumulators that run Park/Clarke transforms in single-cycle MAC throughput. At 40 MIPS, an FOC current loop completes inside 25 us, comfortably supporting 20 kHz electrical switching frequency while leaving MIPS budget for speed PI, communication and housekeeping. Place it between the gate-driver stage and the Hall/encoder feedback interface, using its four PWM Fault inputs to latch on overcurrent events within nanoseconds. Compared with a generic MCU, the dedicated complementary-PWM dead-time generator eliminates firmware overhead and prevents shoot-through in 3-phase inverters up to several kW.
Recommended
Solar Micro-Inverter / Digital PFC
The DSPIC33FJ128MC802-I/SP is well suited to single-phase solar micro-inverters and digital power-factor-correction stages where its DSP engine accelerates average-current-mode control loops, and its 128 KB Flash stores MPPT algorithms plus grid-sync PLL code. The 40 MIPS throughput runs a 50 kHz control loop with substantial headroom for sine-table lookup, THD optimization and anti-islanding checks mandated by IEEE 1547. The 10-bit ADC at 1.1 Msps samples the inductor current and rectified bus voltage synchronously to the PWM carrier, while the configurable logic cell handles zero-crossing detection and frequency multiplier scaling. Pin-select remapping keeps the analog AVSS/AVDD pair isolated from switching nodes on the PCB, an essential consideration for EMC compliance.
Recommended
Industrial Servo and Stepper Drive
For industrial servo amplifiers and stepper drives, the DSPIC33FJ128MC802-I/SP delivers deterministic quadrature decoding through its 5 16-bit capture inputs, and its PWM engine supports microstepping waveforms at sub-millisecond update rates. The DSP MAC computes PID + feed-forward torque control in microseconds, while the 128 KB Flash holds proprietary servo tuning tables and homing profiles. The 21 remappable I/O pins expose encoder index, end-of-travel limits, brake release and serial RS-485 links without external glue logic. Industrial -40C to +85C temperature grade supports factory-floor enclosures, and 5 V-tolerant inputs interface directly to legacy 24 V PLC logic through opto-isolators without level shifters.
Recommended
Switched-Mode Power Supply (SMPS) Control
The DSPIC33FJ128MC802-I/SP drives digital SMPS loops for telecom rectifiers, server VRs and LED drivers by combining the DSP engine's MAC throughput with the dedicated PWM fault inputs and high-resolution 8.5 ns PWM. A 200 kHz voltage-mode or peak-current-mode control loop completes well within 40 MIPS budget, while remaining cycles handle telemetry, PMBus/I2C communication and input voltage feed-forward. The 128 KB Flash accommodates multi-topology firmware (full-bridge, half-bridge, interleaved PFC) configurable at runtime. The 10-bit ADC samples the output voltage and inductor current synchronously to the PWM carrier for clean valley-voltage detection, and the configurable logic cell provides nanosecond-class blanking to suppress transformer ringing.
Recommended
Automotive Body/Sensor ECU
In automotive body and sensor ECUs - HVAC blend doors, mirror positioners, fan controllers - the DSPIC33FJ128MC802-I/SP provides 40 MIPS control, 21 remappable I/O for LIN/CAN transceivers and rotary encoders, plus the dedicated motor-control PWM for brush-style DC motors. Although not AEC-Q100 qualified (the -I/SP grade targets industrial), the design is firmware-compatible with the AEC-Q100 automotive grade variant, allowing prototype-to-production migration. The DSP engine processes wheel-speed and wheel-direction signals in real time for active-suspension preview calculations, while the 16 KB SRAM hosts CANopen or J1939 protocol stacks. Wide -40C to +85C range tolerates under-hood and dashboard thermal environments.
Recommended
HVAC Compressor and Pump Controller
The DSPIC33FJ128MC802-I/SP targets variable-speed HVAC compressor and water-pump controllers because its 8-channel PWM handles power-factor-corrected input plus the BLDC compressor motor with complementary outputs and dead-time control. The 10-bit 1.1 Msps ADC samples both line current and compressor back-EMF simultaneously, while the DSP engine runs sensorless sliding-mode observers to estimate rotor position without Hall sensors. The 128 KB Flash stores multi-refrigerant compressor maps (R-410A, R-32, R-290) and adaptive soft-start routines. Industrial -40C to +85C operation tolerates outdoor condensing-unit enclosures, and the 21 I/O pins accept 0-10 V analog control signals plus Modbus RTU communication.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33FJ128MC802-I/SP — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33FJ128MC802-I/MM | DSPIC33FJ128MC802-E/SP | DSPIC33FJ64MC802-I/SP | DSPIC33FJ32MC302-I/SP | DSPIC33FJ128MC202-I/SP |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | SPDIP-28 | QFN-28 (6x6 mm) - different footprint | SPDIP-28 - same | SPDIP-28 - same | SPDIP-28 - same | SPDIP-28 - same |
| Program Flash | 128 KB | 128 KB | 128 KB | 64 KB (-50%) | 32 KB (-75%) | 128 KB |
| SRAM | 16 KB | 16 KB | 16 KB | 16 KB | 4 KB (-75%) | 8 KB (-50%) |
| MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS |
| Motor-Control PWM | 8 channels, 8.5 ns resolution | 8 channels, 8.5 ns | 8 channels, 8.5 ns | 8 channels, 8.5 ns | 6 channels, 8.5 ns | 6 channels, 8.5 ns |
| ADC | 10-bit, 1.1 Msps, 6 S/H | 10-bit, 1.1 Msps, 6 S/H | 10-bit, 1.1 Msps, 6 S/H | 10-bit, 1.1 Msps, 6 S/H | 10-bit, 1.1 Msps, 6 S/H | 10-bit, 1.1 Msps, 6 S/H |
| Temperature Grade | -40C to +85C (Industrial) | -40C to +85C | -40C to +125C (Extended) | -40C to +85C | -40C to +85C | -40C to +85C |
Key Differentiators
- Highest program Flash in 28-pin SPDIP dsPIC33F family (vs DSPIC33FJ64MC802-I/SP)
- Industrial -40C to +85C operating range vs no extended variant (vs DSPIC33FJ32MC302-I/SP)
- Same family across SPDIP-28 and QFN-28 for design flexibility (vs DSPIC33FJ128MC802-I/MM)
- 8 dedicated motor-control PWM channels with 8.5 ns resolution (vs DSPIC33FJ128MC202-I/SP)
Design Notes
Place a 10 uF bulk tantalum or ceramic plus a 0.1 uF X7R decoupling capacitor within 5 mm of every VDD/AVDD pin pair. Tie all five VSS pins and the exposed pad (where present) to a single uninterrupted ground plane; split the AVSS return only as a moat around the analog ADC traces and stitch back with a single bridge under the device. This avoids ground bounce that would otherwise inject noise into the 10-bit ADC at high PWM switching frequencies. Estimated: input-current budget at 40 MIPS is ~70 mA core, well below the 200 mA VDD rating.
Route the complementary PWM outputs (PWM1H/L, PWM2H/L, PWM3H/L) as matched-length differential pairs to the gate-driver inputs and keep them physically separated from analog signal traces by at least 3 mm or a ground-fill moat. Use the four PWM Fault inputs (FLTAx) for hardware overcurrent latch-off within nanoseconds - never rely on firmware to disable the PWM under fault. The Peripheral Pin Select (PPS) feature lets you remap digital functions away from PWM-bearing pins, simplifying board respins without firmware changes.
Three recurring pitfalls: (1) Forgetting to configure the FPOR power-on reset row tail-feeding configuration register leaves the device in an undefined state at first power-up; always program FPOR in the final hex image. (2) Selecting the internal FRC oscillator without engaging the PLL leaves the device at 7.37 MHz, dropping FOC loop bandwidth by 5x; always enable the PLL with the correct FPLLIDIV/FPLLMUL ratio for 40 MIPS operation. (3) Enabling the ICD/PGD1 pins as general-purpose I/O on RB6/RB7 breaks in-circuit serial programming; reserve these pins for ICSP unless the design is production-final.
The SPDIP-28 package dissipates up to 1 W continuous (theta_JA ~50 C/W on a 4-layer JEDEC test board). Estimated: at 40 MIPS core plus 8 PWM channels at 20 kHz, total power is approximately 0.8 W, yielding a 40 C junction rise at 25 C ambient - acceptable below 60 C ambient. Above 60 C ambient or in enclosed IPM-style modules, mount the device vertically with airflow or drop to the QFN-28 variant (-I/MM) which has a 4x lower theta_JA (~12 C/W).
Compliance Information
Per Microchip product page: Pb-free SPDIP package, RoHS and REACH compliant. Not AEC-Q100 qualified - for automotive AEC-Q100 applications use the automotive-grade dsPIC33FJ128MC802 variant. Halogen-free status not stated in verified data.
