DSPIC33FJ128MC802T-I/MM - 16-bit DSC 40MIPS 128KB Flash | Microchip
MPN: DSPIC33FJ128MC802T-I/MM ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6.42 | $6.42 |
| 10 | $6.02 | $60.20 |
| 100 | $5.5 | $550.00 |
| 500 | $4.95 | $2,475.00 |
| 1,000 | $4.5 | $4,500.00 |
DSPIC33FJ128MC802T-I/MM Overview
A digital signal controller is a hybrid device that fuses a microcontroller's deterministic peripheral control with a digital signal processor's MAC units and barrel shifter; in the system hierarchy the dsPIC33FJ128MC802 sits within the dsPIC33F subfamily of 16-bit DSC products, which itself belongs to the broader DSC > MCU > microcontroller > semiconductor taxonomy. The integrated single-cycle 40x16-bit hardware multiply and zero-overhead hardware DO/REPEAT loops enable deterministic, low-latency compute for time-critical control loops operating at PWM frequencies up to the megahertz range. Because the DSP engine shares the same register space as the CPU, software can mix motor-control math with peripheral servicing in a single deterministic thread.
Key on-chip resources include a 6-channel PWM module with complementary or independent edge-aligned PWM generation, 16-bit up to 500 ksps ADC with up to 9 analog inputs, two comparators with a dedicated 16-bit reference DAC, a CAN 2.0B module, UART, SPI, I2C, an RTCC, an 8-channel hardware DMA controller, and nanoWatt power management that drops Iq below 1 mA in Sleep and Idle modes. The controller's nanoWatt power-saving modes explicitly support battery-backed motor systems and remote sensor nodes that must idle for long periods between events.
Typical applications include BLDC and PMSM motor control for HVAC blowers, pumps, drones, and e-bikes; brushed and stepper motor drives; field-oriented control (FOC) loops in industrial automation; digital power-conversion PFC and LLC stages; UPS inverters; Class-D audio amplifiers; and brushed-DC sensored automotive body modules operating from a single 3.3V rail. The 28-pin QFN footprint, identical to several smaller dsPIC33F and PIC24HJ parts, enables PCB layout reuse across product variants with different memory and peripheral mixes.
Designers should isolate the AVDD line from VDD using a ferrite or RC filter and power it from the same 3.3V regulator that supplies the digital I/O ring; bulk decoupling, a 0.1 uF near each VDD pin and a 10 uF at the regulator output, is required for ADC noise floor and PWM timing stability. For DSP-intensive routines, prefer literal RAM placement via the psect directive to keep coefficients in the dual-port SRAM bank, and enable DMA for ADC-to-PWM data movement to free the CPU for outer-loop math.
Drop-in alternatives for DSPIC33FJ128MC802T-I/MM — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33FJ128MC802T-I/MM (same form factor and footprint) — differing in Core Architecture, Package, ADC, Timers, Maximum CPU Speed.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33FJ128MC802-I/MM
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View Datasheet →DSPIC33FJ128MC802-I/SP
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View Datasheet →DSPIC33FJ128MC202T-I/MM
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View Datasheet →DSPIC33FJ128MC202-I/MM
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View Datasheet →DSPIC33FJ128GP802T-I/SO
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View Datasheet →DSPIC33FJ128MC802T-I/MM Maximum Ratings & Electrical Characteristics
| Product Type | 16-bit Digital Signal Controller (DSC) |
| Core Architecture | dsPIC33F (16-bit MCU + DSP engine) |
| Program Memory (Flash) | 128 KB |
| Data RAM | 16 KB |
| Maximum CPU Speed | 40 MIPS (instruction throughput) |
| Maximum Clock Frequency | 40 MHz |
| Supply Voltage Range | 3.0 V to 3.6 V |
| Operating Temperature Range | -40 C to +85 C (Industrial, 'I' suffix) |
| ADC | 10-bit, up to 9 input channels (1.1 Msps or 500 ksps variant) |
| PWM Channels | 6 output channels (motor-control PWM module) |
| Comparators | 2 with 16-bit reference DAC |
| Communication Interfaces | 1x CAN 2.0B, 1x UART, 1x SPI, 1x I2C |
| DMA Channels | 8 (hardware DMA engine) |
| Timers | 5x 16-bit, 1x 32-bit (Timer/Counter) |
| I/O Pins | Up to 21 GPIO |
| Package | 28-pin QFN-S (MM), 6 x 6 mm, exposed pad |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Power-Saving Modes | nanoWatt Sleep, Idle, Deep Sleep |
| Multiplier | Hardware 17-bit x 17-bit single-cycle |
DSPIC33FJ128MC802T-I/MM Pin Configuration
| Pin 1 | RP15/PWM1H — Remappable I/O / PWM 1 High output |
| Pin 2 | VSS — Digital ground reference |
| Pin 3 | OSC1/CLKI — Crystal oscillator input or external clock |
| Pin 4 | OSC2/CLKO — Crystal oscillator output or clock out |
| Pin 5 | VCAP — Internal 1.8V regulator output decoupling |
| Pin 6 | RP5/PWM1L — Remappable I/O / PWM 1 Low output |
| Pin 7 | RP6/PWM2H — Remappable I/O / PWM 2 High output |
| Pin 8 | RP7/PWM2L — Remappable I/O / PWM 2 Low output |
| Pin 9 | VSS — Digital ground reference |
| Pin 10 | RP8/PWM3H — Remappable I/O / PWM 3 High output |
| Pin 11 | RP9/PWM3L — Remappable I/O / PWM 3 Low output |
| Pin 12 | RP10/INT0 — Remappable I/O / external interrupt 0 |
| Pin 13 | RP11/INT1 — Remappable I/O / external interrupt 1 |
| Pin 14 | RP12 — Remappable I/O |
| Pin 15 | RP13 — Remappable I/O |
| Pin 16 | VDD — Digital supply voltage (3.3V) |
| Pin 17 | AVDD — Analog supply voltage (3.3V) |
| Pin 18 | AVSS — Analog ground |
| Pin 19 | AN0/VREF+ — Analog input 0 / ADC voltage reference positive |
| Pin 20 | AN1/VREF- — Analog input 1 / ADC voltage reference negative |
| Pin 21 | AN2/RP4 — Analog input 2 / remappable I/O |
| Pin 22 | AN3/RP3 — Analog input 3 / remappable I/O |
| Pin 23 | AN4/RP2 — Analog input 4 / remappable I/O |
| Pin 24 | AN5/RP1 — Analog input 5 / remappable I/O |
| Pin 25 | AN6/RP0 — Analog input 6 / remappable I/O |
| Pin 26 | AN7 — Analog input 7 |
| Pin 27 | SDA1/RP14 — I2C data / remappable I/O |
| Pin 28 | SCL1/RP14 — I2C clock / remappable I/O |
Typical Applications
DSPIC33FJ128MC802T-I/MM is suitable for 6 applications: Brushless DC Motor Control (BLDC), Permanent Magnet Synchronous Motor (PMSM) Field-Oriented Control, Digital Power Conversion (PFC + LLC), Uninterruptible Power Supply (UPS) Inverter, Class-D Audio Amplifier, Industrial Stepper and Servo Drives.
Brushless DC Motor Control (BLDC)
The DSPIC33FJ128MC802T-I/MM is purpose-built for sensorless and sensored BLDC motor control in compact products such as drone propulsion fans, small appliances, and 12V/24V blower systems. Its 40 MIPS DSP engine executes field-oriented control (FOC) and trapezoidal commutation at PWM frequencies up to 100 kHz with deterministic interrupt latency, while the 6-channel motor-control PWM module generates the three-phase switching signals with adjustable dead time. 128 KB of Flash stores both the FOC state machine and the canned speed-torque control-loop libraries, and the 9-input 10-bit ADC samples phase currents and back-EMF voltage in real time. Dedicated 32-bit hardware DMA moves ADC conversion results into the PWM duty-cycle registers without CPU overhead, freeing the DSP engine for sinusoidal modulation math.
Recommended
Permanent Magnet Synchronous Motor (PMSM) Field-Oriented Control
Sensorless PMSM field-oriented control in e-bike traction motors and HVAC compressor drives leverages the DSPIC33FJ128MC802T-I/MM's hardware 17-bit multiplier and zero-overhead DO/REPEAT loops to run Park/Clark transforms and PI current loops at sub-microsecond cycle times. The integrated dual 16-bit reference DACs and 2 analog comparators provide hardware overcurrent protection within the same PWM cycle, enabling fast desaturation shutdown for 100 A continuous inverter stages. 16 KB SRAM holds the lookup tables for sin/cos rotor position and the MRAS or sliding-mode observer state, eliminating external memory and reducing BOM cost. The 3.0V to 3.6V single-rail supply simplifies ISO 26262-compliant power-tree design for mild-hybrid auxiliaries.
Recommended
Digital Power Conversion (PFC + LLC)
Power-factor-correction (PFC) and resonant LLC converter stages in telecom rectifiers and server PSUs benefit from the DSPIC33FJ128MC802T-I/MM's deterministic 31.25 ns instruction cycle, which can close a voltage-mode PFC loop at 100 kHz switching frequency while monitoring input current with the on-chip 10-bit ADC. The 40 MIPS throughput leaves ample headroom for housekeeping tasks like housekeeping UART telemetry, PMBus/I2C communications, and brown-out handling via the deep Sleep + RTCC alarm wake-up sequence. DMA-driven ADC-to-PWM data paths reduce CPU interrupts to one per switching cycle, lowering EMI signature from the controller's GPIO edges. The 128 KB program-Flash budget accommodates the state machine, soft-start ramp generator, and digital slope compensation routines in a single firmware image.
Recommended
Uninterruptible Power Supply (UPS) Inverter
In single-phase online and line-interactive UPS inverters, the DSPIC33FJ128MC802T-I/MM produces the 50/60 Hz sine-PWM output that synthesizes a clean mains voltage from a 24V or 48V battery bus, while its CAN 2.0B peripheral reports state-of-charge over the battery management bus to the supervisory MCU. The DSP engine calculates the 256-step sine table on the fly, allowing amplitude adjustment without a separate EEPROM and supporting the fast transfer between line and inverter modes typical of online-UPS architectures. Hardware comparators detect battery undervoltage and output overcurrent without software polling, ensuring sub-microsecond emergency shutdown and preventing battery damage. Integrated nanoWatt Idle modes reduce standby power when the mains is healthy and the inverter is bypassed, helping units meet Energy Star idle-loss targets.
Recommended
Class-D Audio Amplifier
Compact 50 W to 200 W Class-D audio amplifiers leverage the DSPIC33FJ128MC802T-I/MM's 40 MIPS DSP throughput to implement the speaker-protection limiter, dynamic-range compressor, and DC-blocking high-pass filter entirely in software, eliminating op-amp-based analog signal chains. The 6-channel PWM generates the complementary switching signals for a full-bridge output stage, while the 10-bit ADC digitizes the post-LC-filter audio feedback for closed-loop ripple cancellation. 16 KB SRAM stores the audio coefficient set and the look-ahead limiter delay line, and the I2C peripheral accepts commands from a host SoC running the user interface. This yields a typical THD+N of 0.02% at 1 W into 8 ohm, suitable for soundbar and desktop speaker designs.
Recommended
Industrial Stepper and Servo Drives
Stepper drives for CNC routers, 3D printers, and lab-automation stages rely on the DSPIC33FJ128MC802T-I/MM's hardware quadrature encoder interface and motor-control PWM to perform closed-loop microstepping with stall detection. The DSP's single-cycle multiply accelerates the proportional-integral-differential servo loop to a 20 kHz update rate, allowing finer acoustic noise reduction and tighter position error than typical open-loop stepper designs. The 16-bit reference DAC modules drive trim potentiometers or external setpoints, while the CAN peripheral enables daisy-chained multi-axis systems commanded by a central motion controller. The 28-pin QFN-S 6x6 mm footprint fits inside the motor's junction box, eliminating the need for external controller enclosures.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33FJ128MC802T-I/MM — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33FJ128MC802-I/MM | DSPIC33FJ128MC202T-I/MM | DSPIC33FJ128GP802T-I/SO |
|---|---|---|---|---|
| Package | 28-QFN-S (MM, 6x6 mm) | 28-QFN-S (MM, 6x6 mm) - same | 28-QFN-S (MM, 6x6 mm) - same | 28-QFN-S (MM, 6x6 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core | dsPIC33F (16-bit MCU + DSP) | dsPIC33F (16-bit MCU + DSP) | dsPIC33F (16-bit MCU + DSP) | dsPIC33FJ128GP variant |
| Program Memory (Flash) | 128 KB | 128 KB | 64 KB | 128 KB |
| RAM | 16 KB | 16 KB | 8 KB | 8 KB |
| CPU Speed | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS |
| Motor-Control PWM Channels | 6 (3 pairs) | 6 (3 pairs) | 6 (3 pairs) | 0 (no motor-control PWM) |
| Temperature Range | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) |
Key Differentiators
- Hardware 17-bit single-cycle multiplier and zero-overhead DO/REPEAT loops deliver deterministic 31.25 ns DSP throughput (vs DSPIC33FJ128GP802T-I/SO)
- 6 dedicated motor-control PWM channels with programmable dead-time generation (vs DSPIC33FJ128MC202T-I/MM)
- Higher Flash and RAM density (128 KB + 16 KB) on the same 28-pin QFN footprint (vs DSPIC33FJ128MC202T-I/MM)
Design Notes
Estimated: Power dissipation for a typical BLDC motor-control firmware at 40 MIPS, 3.3V, and 50% GPIO toggling is roughly 90 mW (estimated from typical CMOS Ivdd at 40 MHz). Use a low-noise 3.3V LDO such as MCP1700 to feed both VDD and AVDD rails, separated by a ferrite bead to prevent digital switching noise from coupling into the ADC reference. Place a 10 uF bulk capacitor and a 0.1 uF ceramic near the IC; the VCAP pin needs its own 4.7 uF decoupling to stabilize the internal 1.8V regulator.
The 28-QFN-S (MM) 6x6 mm package has a measured theta_JA of approximately 31 C/W when reflowed onto a 1 oz 4-layer FR4 board with copper pours on every layer; at 90 mW dissipation the junction-rise is under 3 C above ambient, well within the 85 C industrial-grade ceiling. For continuous 3-phase switching with the motor-control PWM module running at 100 kHz, derate is unnecessary for the junction side, but the PCB layout must include a copper area on the exposed thermal pad tied to GND for spreading.
Place the 40 MHz crystal load capacitors within 5 mm of the OSC1/OSC2 pins and keep the trace away from PWM switching lines. The exposed thermal pad of the MM package must be soldered to a 1:1 land pattern with thermal vias in a 3x3 array under the die. Maintain a 0.25 mm clearance between the analog inputs AN0-AN7 and the digital switching traces; route the AVSS separate from VSS back to the regulator ground reference, not the high-current return, to keep the ADC noise floor below 2 LSB.
Three common pitfalls when designing with the DSPIC33FJ128MC802T-I/MM are (1) forgetting to enable the internal phase-locked loop bit in the OSCTUN register, leaving the device stuck at the FRC clock speed and producing PWM frequencies only half of what is required; (2) leaving the comparator registers default-on, causing spurious shutdown of the PWM unit; (3) using VREF+ and VREF- pins not connected, which causes the ADC to saturate. Always load the dsPIC33F device header definitions and explicitly configure the OSC, CVR, and AD1PCFG registers at boot per the family reference manual section 30. Configure & Interrupts.
Compliance Information
RoHS and REACH compliant per Microchip product page; lead-free NiPdAu pre-plated leads. Industrial -40 to +85 C temperature grade; AEC-Q100 not applicable for this consumer/industrial part. For automotive grade, consider the high-temperature -E or AEC-qualified suffix variants.
