DSPIC33FJ64GP306-I/PT - 16-bit DSC 40MIPS 64KB Flash | Microchip
MPN: DSPIC33FJ64GP306-I/PT ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.52 | $5.52 |
| 10 | $5.1 | $51.00 |
| 100 | $4.72 | $472.00 |
| 500 | $4.35 | $2,175.00 |
| 1,000 | $4.05 | $4,050.00 |
DSPIC33FJ64GP306-I/PT Overview
A Digital Signal Controller blends the control capabilities of a microcontroller (MCU) with the mathematical throughput of a digital signal processor (DSP) in a single chip. In the semiconductor hierarchy, the DSC sits above general-purpose MCUs for math-intensive control loops and below application processors, making the dsPIC33F family a middle path between Microchip's PIC24 MCUs and dedicated DSPs, with seamless migration between the two.
Key features include a 16-bit modified Harvard architecture executing at 40 MIPS (operating frequency up to 40 MHz), 64 KB self-programming Flash, single-cycle multiply-accumulate DSP engine, and rich connectivity covering I2C, SPI, UART/USART, IrDA and LIN. Peripheral sets include AC'97 audio, DMA, I2S, input capture/output compare channels, and brown-out detect/reset, enabling compact single-chip control designs.
Technically, the dsPIC33F core integrates a DSP engine with dual 40-bit accumulators and hardware divide support, alongside a flexible clock system with on-chip PLL, low-jitter oscillators and fail-safe clock monitoring. The GP (General Purpose) variant emphasizes broad peripheral balance rather than motor-control-specific PWM modules of the MC variants.
Typical applications include digital power supplies and LED drivers, audio signal processing, sensor fusion and industrial automation nodes, and general embedded control where DSP-class math is required without a second processor.
For design, connect all VDD/VSS and AVDD/AVSS pins, and note that multiple PGECx/PGEDx pin pairs exist - use any pair, but keep ICSPCLK and ICSPDAT on the same selected pair for programming and debugging.
This page adds value beyond the datasheet by synthesizing distributor pricing, drop-in same-family alternatives, pinout data, and practical design notes in one citable reference.
Drop-in alternatives for DSPIC33FJ64GP306-I/PT — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33FJ64GP306-I/PT (same form factor and footprint) — differing in Operating Temperature, Package, Mounting Type, Connectivity, Core Architecture.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33FJ64GP306A-I/PT
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33FJ128GP306-I/PT
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$4.55 / Unit
View Datasheet →DSPIC33FJ32GP306-I/PT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ256GP306-I/PT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ256GP506AT-I/PT
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$4.95 / Unit
View Datasheet →DSPIC33FJ64GP306-I/PT Maximum Ratings & Electrical Characteristics
| Core | dsPIC33F (16-bit) |
| Max Speed | 40 MIPS |
| Operating Frequency | 40 MHz |
| Flash Program Memory | 64 KB |
| Core Size | 16-bit |
| Operating Voltage | 3.0 V to 3.6 V |
| Operating Temperature | -40C to +85C (TA) |
| Connectivity | I2C, SPI, UART/USART, IrDA, LIN |
| Peripherals | AC'97, Brown-out Detect/Reset, DMA, I2S |
| Package | 64-TQFP (10x10 mm) |
| Mounting Type | Surface Mount |
| Programming | ICSP (In-Circuit Serial Programming) |
| Debug Interfaces | Multiple PGECx/PGEDx pairs (use as a pair) |
| Migration Path | Seamless to PIC24 MCU and dsPIC30F DSC in similar packages |
| Family | dsPIC33F General Purpose (GP) |
| Supply Voltage Nominal | 3.3 V |
DSPIC33FJ64GP306-I/PT Pin Configuration
| Pin 1 | MCLR — Master clear reset (active low), programming voltage input |
| Pin 2 | AN0/VREF+/CN2/RB0 — Analog input 0 / ADC positive reference / change notification |
| Pin 3 | AN1/VREF-/CN3/RB1 — Analog input 1 / ADC negative reference |
| Pin 4 | AN2/SS1/LVDIN/CN4/RB2 — Analog input 2 / SPI1 slave select / low-voltage detect input |
| Pin 5 | AN3/INDX/CN5/RB3 — Analog input 3 / quadrature index input |
| Pin 6 | AN4/QEA/IC7/CN6/RB4 — Analog input 4 / quadrature A / input capture 7 |
| Pin 7 | AN5/QEB/IC8/CN7/RB5 — Analog input 5 / quadrature B / input capture 8 |
| Pin 8 | AN6/OCFA/RB6 — Analog input 6 / output compare fault A |
| Pin 9 | AN7/RB7 — Analog input 7 / digital I/O |
| Pin 10 | VDD — Positive supply (3.0-3.6 V) |
| Pin 11 | VSS — Ground reference |
| Pin 12 | AN8/RB8 — Analog input 8 / digital I/O |
| Pin 13 | AN9/RB9 — Analog input 9 / digital I/O |
| Pin 14 | AN10/T2CK/RC0 — Analog input 10 / Timer 2 external clock |
| Pin 15 | AN11/T3CK/RC1 — Analog input 11 / Timer 3 external clock |
| Pin 16 | AN12/T4CK/RC2 — Analog input 12 / Timer 4 external clock |
| Pin 17 | AN13/T5CK/RC3 — Analog input 13 / Timer 5 external clock |
| Pin 18 | AN14/CN1/RC4 — Analog input 14 / change notification |
| Pin 19 | AN15/OCFB/CN0/RC5 — Analog input 15 / output compare fault B |
| Pin 20 | VSS — Ground reference |
| Pin 21 | OSC1/CLKI/RC12 — Crystal oscillator input / external clock input |
| Pin 22 | OSC2/CLKO/RC15 — Crystal oscillator output / clock output |
| Pin 23 | VDD — Positive supply (3.0-3.6 V) |
| Pin 24 | SOSCI/CN1/RC13 — Secondary oscillator input (32.768 kHz) / change notification |
| Pin 25 | SOSCO/T1CK/CN0/RC14 — Secondary oscillator output / Timer 1 external clock |
| Pin 26 | RF2/U1RX/SDI2 — UART1 receive / SPI2 data input |
| Pin 27 | RF3/U1TX/SDO2 — UART1 transmit / SPI2 data output |
| Pin 28 | RF7/SDI1 — SPI1 data input |
| Pin 29 | RF0 — General-purpose I/O (UART2/CN remappable per PPS) |
| Pin 30 | RF1 — General-purpose I/O (UART2/CN remappable per PPS) |
| Pin 31 | RD8 — Digital I/O PORTD |
| Pin 32 | RD9 — Digital I/O PORTD |
| Pin 33 | RD10 — Digital I/O PORTD |
| Pin 34 | RD11 — Digital I/O PORTD |
| Pin 35 | VSS — Ground reference |
| Pin 36 | VDD — Positive supply (3.0-3.6 V) |
| Pin 37 | RF6/SDO1 — SPI1 data output |
| Pin 38 | RF5/SCK1 — SPI1 serial clock |
| Pin 39 | RF4/SDA1 — I2C1 data (open drain) |
| Pin 40 | RE0 — Digital I/O PORTE |
| Pin 41 | RE1 — Digital I/O PORTE |
| Pin 42 | RE2 — Digital I/O PORTE |
| Pin 43 | RE3 — Digital I/O PORTE |
| Pin 44 | RE4 — Digital I/O PORTE |
| Pin 45 | RE5 — Digital I/O PORTE |
| Pin 46 | RE6 — Digital I/O PORTE |
| Pin 47 | RE7 — Digital I/O PORTE |
| Pin 48 | AVDD — Analog positive supply - must be connected for ADC |
| Pin 49 | AVSS — Analog ground - must be connected for ADC |
| Pin 50 | RG2 — Digital I/O PORTG |
| Pin 51 | RG3 — Digital I/O PORTG |
| Pin 52 | RD12 — Digital I/O PORTD / change notification |
| Pin 53 | RD13 — Digital I/O PORTD / change notification |
| Pin 54 | RG0 — Digital I/O PORTG |
| Pin 55 | RG1 — Digital I/O PORTG |
| Pin 56 | RD0 — Digital I/O PORTD |
| Pin 57 | RD1 — Digital I/O PORTD |
| Pin 58 | RD2 — Digital I/O PORTD |
| Pin 59 | RD3 — Digital I/O PORTD |
| Pin 60 | RD4 — Digital I/O PORTD |
| Pin 61 | VSS — Ground reference |
| Pin 62 | VDD — Positive supply (3.0-3.6 V) |
| Pin 63 | RD5 — Digital I/O PORTD |
| Pin 64 | RD6 — Digital I/O PORTD |
Typical Applications
DSPIC33FJ64GP306-I/PT is suitable for 6 applications: Digital Power Supplies, Audio Signal Processing, Industrial Automation and Control Nodes, Sensor Fusion and Data Acquisition, Motor-adjacent Embedded Control, Portable and Battery-Powered Instruments.
Digital Power Supplies
The DSPIC33FJ64GP306-I/PT fits digitally controlled power supplies because its 40 MIPS 16-bit core with single-cycle multiply-accumulate executes PID and compensation algorithms at switching frequencies that a standard MCU cannot sustain. ADC input channels (AN0-AN15) sample output voltage and current, while output-compare channels and DMA keep feedback loops deterministic. Running at 3.0-3.6 V with brown-out detect, the DSC supervises its own rail integrity in mission-critical converters. Placed as the supervisory controller between the feedback divider and gate-driver inputs, it adds programmable soft-start, fault logging and adaptive control that fixed-function PWM controllers lack. The trade-off is firmware development effort versus analog-controller simplicity.
Recommended
Audio Signal Processing
The DSPIC33FJ64GP306-I/PT is well suited to embedded audio because it integrates AC'97 and I2S interfaces alongside a DSP engine that performs single-cycle MAC operations, enabling FIR/IIR filtering, mixing and effects at 40 MIPS. For a Bluetooth-speaker or intercom product, the DSC connects directly to an audio codec via I2S, processes the stream in firmware, and manages system control on the same chip - eliminating a separate MCU. At 64 KB Flash, mid-complexity effect chains fit; use the 128 KB GP306 sibling for heavier processing. The trade-off versus a dedicated audio DSP is lower raw throughput, offset by lower system cost and single-chip integration.
Recommended
Industrial Automation and Control Nodes
In factory automation, the DSPIC33FJ64GP306-I/PT serves as an intelligent sensor/actuator node: its -40C to +85C rating survives panel environments, the 64-TQFP provides abundant I/O through PORTB/PORTC/PORTD/PORTE/PORTF/PORTG, and connectivity covers I2C, SPI, UART, IrDA and LIN for PLC backbones and field buses. The DMA engine offloads data movement so the 40 MIPS core focuses on control algorithms, while input-capture channels timestamp encoder or sensor pulses in hardware. Deployed between analog sensors (on AN0-AN15) and a RS-485/LIN transceiver, the DSC implements local decision logic with deterministic timing. The industrial temperature suffix -I makes it appropriate for unconditioned factory floors.
Recommended
Sensor Fusion and Data Acquisition
The DSPIC33FJ64GP306-I/PT handles multi-sensor data acquisition because its 16-channel ADC input set (AN0-AN15) with external VREF+ support samples several analog sources synchronously, and the DSP engine executes calibration, filtering and FFT tasks in real time at 40 MIPS. In a vibration-monitoring or predictive-maintenance node, accelerometer and microphone signals enter through analog channels, DMA streams samples to RAM without CPU intervention, and the accumulated results ship over UART or SPI to a host. The 64 KB Flash stores both firmware and calibration tables; the 128 KB variant fits more buffers or on-device FFT tables. Brown-out detect guarantees data integrity through supply dips.
Recommended
Motor-adjacent Embedded Control
While the MC-series dsPIC33F parts carry dedicated motor PWM modules, the general-purpose DSPIC33FJ64GP306-I/PT still drives motion and positioning subsystems - such as stepper drivers, DC-servo supervisory loops, and BLDC host controllers - using output-compare channels and quadrature interfaces (QEA/QEB and INDX on RB3-RB5) that decode encoder feedback in hardware. At 40 MIPS, the DSC closes current loops fast enough for small motor applications while managing communication with a higher-level controller over LIN, UART or SPI. Designers needing 3-phase high-resolution PWM should step to the MC family, but for supervisory motion logic the GP306 offers the same core in a flexible general-purpose I/O arrangement.
Recommended
Portable and Battery-Powered Instruments
The DSPIC33FJ64GP306-I/PT suits handheld instruments - measurement meters, portable loggers, test accessories - by combining 3.0-3.6 V single-rail operation, integrated brown-out supervision, and a fail-safe clock system with PLL from a crystal or internal oscillator. The 64-TQFP 10x10 mm footprint balances I/O density against board area, and ICSP programming via any PGECx/PGEDx pair simplifies field firmware updates with two-wire tools like MPLAB SNAP. Its 40 MIPS DSP engine performs on-device averaging, filtering and unit conversion so raw readings upload over UART/USB-bridge links. Versus a PIC24 MCU, the added DSP headroom lets the same firmware grow into spectrum or waveform analysis features later.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33FJ64GP306-I/PT — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33FJ64GP306A-I/PT | DSPIC33FJ128GP306-I/PT | DSPIC33FJ32GP306-I/PT | DSPIC33FJ256GP306-I/PT | DSPIC33FJ256GP506AT-I/PT |
|---|---|---|---|---|---|---|
| Package | 64-TQFP (10x10 mm) | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core / Speed | dsPIC33F, 40 MIPS | dsPIC33F, 40 MIPS | dsPIC33F, 40 MIPS | dsPIC33F, 40 MIPS | dsPIC33F, 40 MIPS | dsPIC33F, 40 MIPS |
| Flash Memory | 64 KB | 64 KB | 128 KB | 32 KB | 256 KB | 256 KB |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C (I grade) |
| Operating Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
Key Differentiators
- Cost-optimized 64 KB point in the GP306 pinout (vs DSPIC33FJ256GP306-I/PT)
- Base-revision errata risk vs A-step (vs DSPIC33FJ64GP306A-I/PT)
- Right-sized memory for mid-complexity firmware (vs DSPIC33FJ128GP306-I/PT)
Design Notes
Connect ALL VDD (pins 10, 23, 36, 62), VSS (pins 11, 20, 35, 61), AVDD (pin 48) and AVSS (pin 49) pins. Per Northern Software dsPIC33FJ64GP306 guidance and Microchip programming documentation, leaving even one power pin unconnected can cause ICSP programming to fail. Decouple each VDD pin pair with 0.1 uF ceramic capacitors placed within 2-3 mm of the pin, plus one bulk 10 uF capacitor per supply domain. Keep the analog ground island under AVSS/AN pins separate from the digital return until a single star point.
The device offers multiple PGECx/PGEDx programming pin pairs. You may use any pair, but ICSPCLK (PGECx) and ICSPDAT (PGEDx) must be on the SAME selected pair - mixing PGEC2 with PGED1 will fail silently during programming. Route the chosen pair to your programming header with short traces and avoid loading them with LEDs or pull-downs. Also configure MCLR with a 10k pull-up to VDD; MCLR doubles as the high-voltage programming entry pin, so do not clamp it with a diode to VDD.
Operate from a regulated 3.3 V rail within the 3.0-3.6 V datasheet window. Estimated: at 40 MIPS with moderate I/O loading, core current is typically in the tens of mA range - budget the rail using your firmware's measured current, not the headline 40 MIPS figure. The secondary oscillator (SOSCI/SOSCO, pins 24-25) can run a 32.768 kHz crystal for RTCC while the primary 40 MHz clock derives from OSC1/OSC2 (pins 21-22) with the internal PLL; ensure crystal load capacitors match the crystal datasheet, typically 10-15 pF.
For ADC accuracy, keep analog traces (AN0-AN15, pins 2-19) away from SPI/UART switching lines on PORTF/PORTG, and reference the ADC divider to the clean AVDD/AVSS domain (pins 48-49). Use VREF+ (pin 2) with a precision reference such as a bandgap-based IC if better than the supply-rail-referenced accuracy is needed. The 64-TQFP exposed-lead footprint needs standard 0.2 mm pitch land patterns per IPC-7351 practices; verify paste stencil aperture to prevent bridging on the fine-pitch corner pins.
Compliance Information
Lead-free standard for current Microchip production; -I temperature grade indicates industrial -40C to +85C. Automotive AEC-Q100 status not stated in provided data - use the AT-suffix variant for automotive needs. RoHS/REACH certificates should be requested from Microchip.
