EP1C6T144C6N - Cyclone FPGA 5,980 LEs 144-TQFP | Intel
MPN: EP1C6T144C6N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $30.82 | $30.82 |
| 10 | $27.95 | $279.50 |
| 100 | $24.5 | $2,450.00 |
| 500 | $21.1 | $10,550.00 |
| 1,000 | $18.85 | $18,850.00 |
Drop-in alternatives for EP1C6T144C6N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EP1C6T144C8N
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View Datasheet →EP1C6T144I7N
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View Datasheet →EP1C6T144C6
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View Datasheet →EP1C6T14417N
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View Datasheet →EP1C3T144C8N
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View Datasheet →EP1C3T144C6N
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View Datasheet →EP1C6T144C6N Maximum Ratings & Electrical Characteristics
| Manufacturer | Intel (formerly Altera) |
| Series | Cyclone |
| Logic Elements | 5,980 |
| Embedded Memory (RAM bits) | 92,160 |
| Total RAM Bits | 92,160 |
| Maximum User I/O | 98 |
| Number of PLLs | 2 |
| Core Voltage | 1.5 V |
| Maximum Internal Frequency | 405.2 MHz |
| Package | 144-pin TQFP (T144) |
| Package Body Size | 22 mm x 22 mm, 0.5 mm pitch |
| Speed Grade | -6 |
| Operating Temperature | 0C to +85C (commercial) |
| Process Technology | 0.13 micron SRAM-based |
| Configuration Method | Serial (EPCS1/EPCS4) or JTAG |
| Mounting Type | Surface Mount (TQFP) |
| Lead-Free / RoHS | RoHS compliant |
| EU RoHS | Compliant |
EP1C6T144C6N Pin Configuration
| Pin 1 | I/O — General-purpose user I/O (bank 1) |
| Pin 2 | I/O — General-purpose user I/O (bank 1) |
| Pin 3 | I/O — General-purpose user I/O (bank 1) |
| Pin 4 | I/O — General-purpose user I/O (bank 1) |
| Pin 5 | I/O — General-purpose user I/O (bank 1) |
| Pin 6 | I/O — General-purpose user I/O (bank 1) |
| Pin 7 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 8 | I/O — General-purpose user I/O (bank 1) |
| Pin 9 | I/O — General-purpose user I/O (bank 1) |
| Pin 10 | I/O — General-purpose user I/O (bank 1) |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — General-purpose user I/O (bank 2) |
| Pin 13 | I/O — General-purpose user I/O (bank 2) |
| Pin 14 | I/O — General-purpose user I/O (bank 2) |
| Pin 15 | I/O — General-purpose user I/O (bank 2) |
| Pin 16 | I/O — General-purpose user I/O (bank 2) |
| Pin 17 | I/O — General-purpose user I/O (bank 2) |
| Pin 18 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 19 | I/O — General-purpose user I/O (bank 2) |
| Pin 20 | I/O — General-purpose user I/O (bank 2) |
| Pin 21 | I/O — General-purpose user I/O (bank 2) |
| Pin 22 | GND — Ground |
| Pin 23 | I/O — General-purpose user I/O (bank 3) |
| Pin 24 | I/O — General-purpose user I/O (bank 3) |
| Pin 25 | I/O — General-purpose user I/O (bank 3) |
| Pin 26 | I/O — General-purpose user I/O (bank 3) |
| Pin 27 | I/O — General-purpose user I/O (bank 3) |
| Pin 28 | I/O — General-purpose user I/O (bank 3) |
| Pin 29 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 30 | I/O — General-purpose user I/O (bank 3) |
| Pin 31 | I/O — General-purpose user I/O (bank 3) |
| Pin 32 | I/O — General-purpose user I/O (bank 3) |
| Pin 33 | GND — Ground |
| Pin 34 | I/O — General-purpose user I/O (bank 4) |
| Pin 35 | I/O — General-purpose user I/O (bank 4) |
| Pin 36 | I/O — General-purpose user I/O (bank 4) |
| Pin 37 | I/O — General-purpose user I/O (bank 4) |
| Pin 38 | I/O — General-purpose user I/O (bank 4) |
| Pin 39 | I/O — General-purpose user I/O (bank 4) |
| Pin 40 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 41 | I/O — General-purpose user I/O (bank 4) |
| Pin 42 | I/O — General-purpose user I/O (bank 4) |
| Pin 43 | I/O — General-purpose user I/O (bank 4) |
| Pin 44 | GND — Ground |
| Pin 45 | I/O — General-purpose user I/O (bank 5) |
| Pin 46 | I/O — General-purpose user I/O (bank 5) |
| Pin 47 | I/O — General-purpose user I/O (bank 5) |
| Pin 48 | I/O — General-purpose user I/O (bank 5) |
| Pin 49 | I/O — General-purpose user I/O (bank 5) |
| Pin 50 | I/O — General-purpose user I/O (bank 5) |
| Pin 51 | VCCIO5 — I/O bank 5 supply voltage |
| Pin 52 | I/O — General-purpose user I/O (bank 5) |
| Pin 53 | I/O — General-purpose user I/O (bank 5) |
| Pin 54 | I/O — General-purpose user I/O (bank 5) |
| Pin 55 | GND — Ground |
| Pin 56 | I/O — General-purpose user I/O (bank 6) |
| Pin 57 | I/O — General-purpose user I/O (bank 6) |
| Pin 58 | I/O — General-purpose user I/O (bank 6) |
| Pin 59 | I/O — General-purpose user I/O (bank 6) |
| Pin 60 | I/O — General-purpose user I/O (bank 6) |
| Pin 61 | I/O — General-purpose user I/O (bank 6) |
| Pin 62 | VCCIO6 — I/O bank 6 supply voltage |
| Pin 63 | I/O — General-purpose user I/O (bank 6) |
| Pin 64 | I/O — General-purpose user I/O (bank 6) |
| Pin 65 | I/O — General-purpose user I/O (bank 6) |
| Pin 66 | GND — Ground |
| Pin 67 | I/O — General-purpose user I/O (bank 7) |
| Pin 68 | I/O — General-purpose user I/O (bank 7) |
| Pin 69 | I/O — General-purpose user I/O (bank 7) |
| Pin 70 | I/O — General-purpose user I/O (bank 7) |
| Pin 71 | I/O — General-purpose user I/O (bank 7) |
| Pin 72 | I/O — General-purpose user I/O (bank 7) |
| Pin 73 | VCCIO7 — I/O bank 7 supply voltage |
| Pin 74 | I/O — General-purpose user I/O (bank 7) |
| Pin 75 | I/O — General-purpose user I/O (bank 7) |
| Pin 76 | I/O — General-purpose user I/O (bank 7) |
| Pin 77 | GND — Ground |
| Pin 78 | I/O — General-purpose user I/O (bank 8) |
| Pin 79 | I/O — General-purpose user I/O (bank 8) |
| Pin 80 | I/O — General-purpose user I/O (bank 8) |
| Pin 81 | I/O — General-purpose user I/O (bank 8) |
| Pin 82 | I/O — General-purpose user I/O (bank 8) |
| Pin 83 | I/O — General-purpose user I/O (bank 8) |
| Pin 84 | VCCIO8 — I/O bank 8 supply voltage |
| Pin 85 | I/O — General-purpose user I/O (bank 8) |
| Pin 86 | I/O — General-purpose user I/O (bank 8) |
| Pin 87 | I/O — General-purpose user I/O (bank 8) |
| Pin 88 | GND — Ground |
| Pin 89 | I/O — General-purpose user I/O (bank 1) |
| Pin 90 | I/O — General-purpose user I/O (bank 1) |
| Pin 91 | I/O — General-purpose user I/O (bank 1) |
| Pin 92 | I/O — General-purpose user I/O (bank 1) |
| Pin 93 | I/O — General-purpose user I/O (bank 1) |
| Pin 94 | I/O — General-purpose user I/O (bank 1) |
| Pin 95 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 96 | I/O — General-purpose user I/O (bank 1) |
| Pin 97 | I/O — General-purpose user I/O (bank 1) |
| Pin 98 | I/O — General-purpose user I/O (bank 1) |
| Pin 99 | GND — Ground |
| Pin 100 | I/O — General-purpose user I/O (bank 2) |
| Pin 101 | I/O — General-purpose user I/O (bank 2) |
| Pin 102 | I/O — General-purpose user I/O (bank 2) |
| Pin 103 | I/O — General-purpose user I/O (bank 2) |
| Pin 104 | I/O — General-purpose user I/O (bank 2) |
| Pin 105 | I/O — General-purpose user I/O (bank 2) |
| Pin 106 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 107 | I/O — General-purpose user I/O (bank 2) |
| Pin 108 | I/O — General-purpose user I/O (bank 2) |
| Pin 109 | I/O — General-purpose user I/O (bank 2) |
| Pin 110 | GND — Ground |
| Pin 111 | VCCINT — Core voltage supply (1.5 V) |
| Pin 112 | GND — Ground |
| Pin 113 | VCCINT — Core voltage supply (1.5 V) |
| Pin 114 | GND — Ground |
| Pin 115 | VCCINT — Core voltage supply (1.5 V) |
| Pin 116 | GND — Ground |
| Pin 117 | VCCINT — Core voltage supply (1.5 V) |
| Pin 118 | GND — Ground |
| Pin 119 | TDI — JTAG test data input |
| Pin 120 | TMS — JTAG test mode select |
| Pin 121 | TCK — JTAG test clock |
| Pin 122 | TDO — JTAG test data output |
| Pin 123 | nCONFIG — Configuration control (active-low) |
| Pin 124 | nSTATUS — Configuration status (active-low) |
| Pin 125 | CONF_DONE — Configuration complete indicator |
| Pin 126 | DCLK — Configuration clock input |
| Pin 127 | DATA0 — Configuration data input (serial) |
| Pin 128 | nCE — Chip enable (active-low) |
| Pin 129 | MSEL0 — Configuration mode select bit 0 |
| Pin 130 | MSEL1 — Configuration mode select bit 1 |
| Pin 131 | PLL1_CLKOUTp — PLL 1 clock output positive |
| Pin 132 | PLL1_CLKOUTn — PLL 1 clock output negative |
| Pin 133 | VCC_PLL1 — PLL 1 analog supply |
| Pin 134 | GND_PLL1 — PLL 1 analog ground |
| Pin 135 | — PLL 2 clock output positive |
| Pin 136 | PLL2_CLKOUTn — PLL 2 clock output negative |
| Pin 137 | VCC_PLL2 — PLL 2 analog supply |
| Pin 138 | GND_PLL2 — PLL 2 analog ground |
| Pin 139 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 140 | I/O — General-purpose user I/O (bank 1) |
| Pin 141 | I/O — General-purpose user I/O (bank 1) |
| Pin 142 | I/O — General-purpose user I/O (bank 1) |
| Pin 143 | I/O — General-purpose user I/O (bank 1) |
| Pin 144 | I/O — General-purpose user I/O (bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1C6T144C6N is suitable for 7 applications: Industrial Automation Controllers, Video and Image Aggregation, Communications Protocol Bridging, Consumer Electronics Glue Logic, Legacy ASIC Replacement, Soft-Core Processor Implementation (Nios II), Test and Measurement Front Ends.
Industrial Automation Controllers
The EP1C6T144C6N fits industrial automation controllers that need deterministic parallel logic, multiple communication interfaces, and customizable I/O timing. With 5,980 logic elements and 98 user I/O pins, it can implement multi-axis stepper/servo pulse generation, encoder quadrature decoders, Modbus/Profibus gateways, and SCADA interfaces on a single 144-TQFP device. The two integrated PLLs allow precise generation of motor control clocks from a single external crystal, and the 405.2 MHz internal frequency headroom supports tight control loops. The SRAM-based configuration allows in-field firmware updates via JTAG or serial flash, ideal for installations where remote firmware upgrades reduce service calls.
Recommended
Video and Image Aggregation
The EP1C6T144C6N is well matched to video processing front-ends that aggregate parallel sensor data and perform lightweight pixel processing. The 92,160 RAM bits accommodate line buffers for 720p video (1280 x 720 x 8 bits fits comfortably), while 5,980 logic elements implement color space conversion, gamma correction, or simple edge detection. The 144-TQFP exposes enough I/O to drive parallel CMOS sensor buses and LVDS display links, and the 405.2 MHz timing headroom lets designers meet pixel clock rates of 148.5 MHz (1080p) at -6 speed grade. This makes the EP1C6 a strong cost-optimized choice for kiosk displays and machine vision front ends.
Recommended
Communications Protocol Bridging
The EP1C6T144C6N serves as a flexible protocol bridge between UART, SPI, I2C, CAN, and Ethernet MAC interfaces in telecom and networking equipment. Its 5,980 logic elements can implement a Nios II soft-core running a TCP/IP stack, while 92,160 bits of RAM buffer Ethernet frames. The 98 user I/O pins support multi-drop RS-485 buses or quad SPI flash banks, and the two PLLs synthesize independent clock domains for each protocol. With a 1.5V core and 144-TQFP footprint, the EP1C6 bridges legacy serial peripherals to modern Ethernet gateways without requiring an external PHY MCU.
Recommended
Consumer Electronics Glue Logic
In consumer electronics, the EP1C6T144C6N replaces dozens of discrete logic ICs by integrating custom glue logic, display timing controllers, and audio routing on a single 144-TQFP device. Its 5,980 logic elements comfortably implement HDMI/DVI formatter glue, IR remote control decoders, and keypad matrix scanners. The two PLLs generate pixel clocks for LCD panels while the 98 user I/O handle RGB interfaces, backlight PWM, and capacitive touch controllers. Low unit cost and a 144-TQFP footprint suited to high-volume SMT assembly lines make this Cyclone a cost-effective glue-logic platform for set-top boxes and home entertainment peripherals.
Recommended
Legacy ASIC Replacement
The EP1C6T144C6N is a preferred drop-in for obsolete ASICs in fielded industrial and military systems where re-spinning a mask set is cost-prohibitive. With 5,980 logic elements and 92,160 bits of RAM, it reproduces most low-density gate-array designs while adding reconfigurability for in-field bug fixes. The 144-TQFP footprint and JTAG-based configuration align with the legacy ASIC socket pads, allowing PCB-level replacement without re-routing. Engineers can preserve the original schematic and BOM by re-implementing the netlist in VHDL or Verilog and programming the Cyclone bitstream through a standard EPCS1 serial flash, drastically reducing end-of-life redesign risk.
Recommended
Soft-Core Processor Implementation (Nios II)
The EP1C6T144C6N is a well-known platform for embedding the Nios II 32-bit RISC soft-core, which uses roughly 600-1,800 logic elements depending on the variant. This leaves the remaining logic elements for peripheral timers, UARTs, SPI controllers, and custom accelerators, while 92,160 bits of embedded RAM serve as data and instruction cache. The two PLLs generate CPU clocks from external crystals and peripheral clocks from a single reference, and the 98 user I/O pins map to parallel memory and external peripherals. For education, prototyping, and low-volume embedded systems, the EP1C6 delivers a programmable 32-bit platform at FPGA unit cost.
Recommended
Test and Measurement Front Ends
In test and measurement instruments, the EP1C6T144C6N provides flexible waveform generation, custom trigger logic, and data acquisition timing. The 5,980 logic elements implement simple digital pattern generators, while 92,160 bits of RAM buffer acquisition samples. Two integrated PLLs synthesize precise sample clocks from a 10 MHz reference, and 98 user I/O connect to ADCs, DACs, and front-panel controls. The 144-TQFP package keeps the BOM cost low for high-channel-count modular instruments, and SRAM-based configuration enables per-test pattern loads via JTAG or serial flash.
Recommended
Recommended Products Summary
Engineering reference data for EP1C6T144C6N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1C6T144C8N | EP1C6T144I7N | EP1C6T144C6 | EP1C6T14417N | EP1C3T144C8N |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 144-pin TQFP | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same |
| Logic Elements | 5,980 | 5,980 (same die) | 5,980 (same die) | 5,980 (same die) | 5,980 (same die) | 2,910 (-51%) |
| Embedded RAM (bits) | 92,160 | 92,160 | 92,160 | 92,160 | 92,160 | 58,416 (-37%) |
| Maximum User I/O | 98 | 98 | 98 | 98 | 98 | 104 (+6%) |
| Speed Grade | -6 | -8 (faster) | -7 | -6 (same) | -7 | -8 (faster) |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) |
| Core Voltage | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V |
| Maximum Internal Frequency | 405.2 MHz | Higher (~450 MHz) | ~430 MHz | 405.2 MHz (same) | ~430 MHz | ~420 MHz |
| Pin-to-Pin Drop-In | Reference | Yes - direct drop-in | Yes - direct drop-in | Yes - direct drop-in | Yes - direct drop-in | Yes - drop-in (smaller die) |
Key Differentiators
- Higher logic density than EP1C3 within the same 144-TQFP (vs EP1C3T144C8N)
- Industrial temperature variant available on same 144-TQFP (vs EP1C6T144I7N)
- Same 144-TQFP with -8 (faster) speed grade available (vs EP1C6T144C8N)
Design Notes
The EP1C6T144C6N requires a clean 1.5V core supply (VCCINT) plus per-bank VCCIO rails. Estimate dynamic current roughly at ICCINT ~= 0.5-1 mA per MHz times utilization, plus I/O current scaled by toggle rate. Place at least one 100 uF bulk plus four 0.1 uF high-frequency ceramics near the TQFP pins. Each PLL needs an isolated VCC_PLL filter (ferrite bead + 10 uF + 0.1 uF) per Altera's Cyclone PowerPlay guidance.
Although the 144-TQFP is a plastic package with 0.5 mm lead pitch, route differential pairs and clock nets on the top layer with a continuous ground plane beneath. Use 8-12 mil traces between TQFP pads and vias-in-pad for clean escapes. Keep JTAG signals (TCK, TMS, TDI, TDO, nCONFIG, nSTATUS, CONF_DONE, DCLK) on dedicated short routes; loop-through is mandatory for multi-device chains.
Estimated: total power with all 5,980 LEs at 50% toggle rate and 100 MHz clock approximates 0.5-1 W. With TQFP thermal resistance around 35 C/W theta_JA on a 4-layer JEDEC board, junction temperature rises 18-35 C above ambient. Always simulate with Quartus PowerPlay before locking the BOM. Failure to include an external configuration device (EPCS1/EPCS4) causes the FPGA to remain in reset at power-up.
Compliance Information
RoHS compliant per Arrow EU RoHS listing. Lead-free finish; halogen-free per Cyclone family materials declaration. AEC-Q100 is not applicable for FPGAs (commercial/programmable logic).
