EP1C6T144C8N - Cyclone FPGA 5980 LE 144-TQFP | Intel / Altera
MPN: EP1C6T144C8N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $23.07 | $23.07 |
| 10 | $20.5 | $205.00 |
| 100 | $17.2 | $1,720.00 |
| 500 | $14.8 | $7,400.00 |
| 1,000 | $12.95 | $12,950.00 |
Drop-in alternatives for EP1C6T144C8N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EP1C6T144C8N Maximum Ratings & Electrical Characteristics
| Series | Cyclone® |
| Family | Cyclone I |
| Logic Elements (LE) | 5,980 |
| Logic Array Blocks (LAB) | 598 |
| Total RAM Bits | 92,160 |
| User I/O Pins | 98 |
| Number of I/O Banks | 4 |
| PLLs | 2 |
| Maximum Internal Frequency | 275 MHz |
| Speed Grade | C8 (commercial) |
| Core Voltage (VCCINT) | 1.425 V to 1.575 V (typ. 1.5 V) |
| Process Technology | 0.13 µm all-layer copper SRAM |
| Package | 144-pin TQFP |
| Mounting Type | Surface Mount |
| Operating Temperature | 0°C to +85°C (commercial) |
| Configuration Method | Active Serial (EPCS), Passive Serial, JTAG |
| MSL Level | 3 (per JEDEC J-STD-020) |
| RoHS Status | Compliant |
EP1C6T144C8N Pin Configuration
| Pin 1 | I/O — User I/O pin (Bank 1) |
| Pin 2 | I/O — User I/O pin (Bank 1) |
| Pin 3 | I/O — User I/O pin (Bank 1) |
| Pin 4 | I/O — User I/O pin (Bank 1) |
| Pin 5 | I/O — User I/O pin (Bank 1) |
| Pin 6 | VCCIO1 — I/O Bank 1 supply voltage |
| Pin 7 | I/O — User I/O pin (Bank 1) |
| Pin 8 | I/O — User I/O pin (Bank 1) |
| Pin 9 | I/O — User I/O pin (Bank 1) |
| Pin 10 | GND — Ground |
| Pin 11 | I/O — User I/O pin (Bank 2) |
| Pin 12 | I/O — User I/O pin (Bank 2) |
| Pin 13 | I/O — User I/O pin (Bank 2) |
| Pin 14 | I/O — User I/O pin (Bank 2) |
| Pin 15 | VCCIO2 — I/O Bank 2 supply voltage |
| Pin 16 | I/O — User I/O pin (Bank 2) |
| Pin 17 | I/O — User I/O pin (Bank 2) |
| Pin 18 | I/O — User I/O pin (Bank 2) |
| Pin 19 | I/O — User I/O pin (Bank 2) |
| Pin 20 | GND — Ground |
| Pin 21 | I/O — User I/O pin (Bank 2) |
| Pin 22 | I/O — User I/O pin (Bank 2) |
| Pin 23 | I/O — User I/O pin (Bank 2) |
| Pin 24 | I/O — User I/O pin (Bank 2) |
| Pin 25 | I/O — User I/O pin (Bank 2) |
| Pin 26 | VCCINT — Core supply voltage (1.5 V) |
| Pin 27 | I/O — User I/O pin (Bank 2) |
| Pin 28 | I/O — User I/O pin (Bank 2) |
| Pin 29 | I/O — User I/O pin (Bank 2) |
| Pin 30 | GND — Ground |
| Pin 31 | I/O — User I/O pin (Bank 2) |
| Pin 32 | I/O — User I/O pin (Bank 2) |
| Pin 33 | I/O — User I/O pin (Bank 2) |
| Pin 34 | I/O — User I/O pin (Bank 2) |
| Pin 35 | I/O — User I/O pin (Bank 2) |
| Pin 36 | VCCIO2 — I/O Bank 2 supply voltage |
| Pin 37 | I/O — User I/O pin (Bank 2) |
| Pin 38 | I/O — User I/O pin (Bank 2) |
| Pin 39 | I/O — User I/O pin (Bank 2) |
| Pin 40 | I/O — User I/O pin (Bank 2) |
| Pin 41 | I/O — User I/O pin (Bank 2) |
| Pin 42 | GND — Ground |
| Pin 43 | I/O — User I/O pin (Bank 3) |
| Pin 44 | I/O — User I/O pin (Bank 3) |
| Pin 45 | I/O — User I/O pin (Bank 3) |
| Pin 46 | I/O — User I/O pin (Bank 3) |
| Pin 47 | VCCIO3 — I/O Bank 3 supply voltage |
| Pin 48 | I/O — User I/O pin (Bank 3) |
| Pin 49 | I/O — User I/O pin (Bank 3) |
| Pin 50 | I/O — User I/O pin (Bank 3) |
| Pin 51 | I/O — User I/O pin (Bank 3) |
| Pin 52 | GND — Ground |
| Pin 53 | I/O — User I/O pin (Bank 3) |
| Pin 54 | I/O — User I/O pin (Bank 3) |
| Pin 55 | I/O — User I/O pin (Bank 3) |
| Pin 56 | I/O — User I/O pin (Bank 3) |
| Pin 57 | I/O — User I/O pin (Bank 3) |
| Pin 58 | VCCINT — Core supply voltage (1.5 V) |
| Pin 59 | I/O — User I/O pin (Bank 3) |
| Pin 60 | I/O — User I/O pin (Bank 3) |
| Pin 61 | I/O — User I/O pin (Bank 3) |
| Pin 62 | GND — Ground |
| Pin 63 | I/O — User I/O pin (Bank 3) |
| Pin 64 | I/O — User I/O pin (Bank 3) |
| Pin 65 | I/O — User I/O pin (Bank 3) |
| Pin 66 | I/O — User I/O pin (Bank 3) |
| Pin 67 | I/O — User I/O pin (Bank 3) |
| Pin 68 | VCCIO3 — I/O Bank 3 supply voltage |
| Pin 69 | I/O — User I/O pin (Bank 3) |
| Pin 70 | I/O — User I/O pin (Bank 3) |
| Pin 71 | I/O — User I/O pin (Bank 3) |
| Pin 72 | I/O — User I/O pin (Bank 3) |
| Pin 73 | I/O — User I/O pin (Bank 3) |
| Pin 74 | GND — Ground |
| Pin 75 | I/O — User I/O pin (Bank 4) |
| Pin 76 | I/O — User I/O pin (Bank 4) |
| Pin 77 | I/O — User I/O pin (Bank 4) |
| Pin 78 | I/O — User I/O pin (Bank 4) |
| Pin 79 | VCCIO4 — I/O Bank 4 supply voltage |
| Pin 80 | I/O — User I/O pin (Bank 4) |
| Pin 81 | I/O — User I/O pin (Bank 4) |
| Pin 82 | I/O — User I/O pin (Bank 4) |
| Pin 83 | I/O — User I/O pin (Bank 4) |
| Pin 84 | GND — Ground |
| Pin 85 | nCONFIG — Configuration start (active low) |
| Pin 86 | nSTATUS — Configuration status (active low) |
| Pin 87 | CONF_DONE — Configuration complete indicator |
| Pin 88 | TCK — JTAG test clock |
| Pin 89 | TMS — JTAG test mode select |
| Pin 90 | TDO — JTAG test data out |
| Pin 91 | TDI — JTAG test data in |
| Pin 92 | VCCIO4 — I/O Bank 4 supply voltage |
| Pin 93 | MSEL0 — Configuration mode select 0 |
| Pin 94 | MSEL1 — Configuration mode select 1 |
| Pin 95 | MSEL2 — Configuration mode select 2 |
| Pin 96 | nCE — Chip enable (active low) |
| Pin 97 | DCLK — Configuration clock (Passive Serial) |
| Pin 98 | DATA0 — Configuration data input |
| Pin 99 | nCSO — Active Serial chip select out |
| Pin 100 | ASDO — Active Serial data out |
| Pin 101 | VCCINT — Core supply voltage (1.5 V) |
| Pin 102 | GND — Ground |
| Pin 103 | I/O — User I/O pin (Bank 4) |
| Pin 104 | I/O — User I/O pin (Bank 4) |
| Pin 105 | I/O — User I/O pin (Bank 4) |
| Pin 106 | I/O — User I/O pin (Bank 4) |
| Pin 107 | I/O — User I/O pin (Bank 4) |
| Pin 108 | I/O — User I/O pin (Bank 4) |
| Pin 109 | I/O — User I/O pin (Bank 4) |
| Pin 110 | VCCIO4 — I/O Bank 4 supply voltage |
| Pin 111 | I/O — User I/O pin (Bank 4) |
| Pin 112 | I/O — User I/O pin (Bank 4) |
| Pin 113 | I/O — User I/O pin (Bank 1) |
| Pin 114 | I/O — User I/O pin (Bank 1) |
| Pin 115 | I/O — User I/O pin (Bank 1) |
| Pin 116 | I/O — User I/O pin (Bank 1) |
| Pin 117 | VCCIO1 — I/O Bank 1 supply voltage |
| Pin 118 | I/O — User I/O pin (Bank 1) |
| Pin 119 | I/O — User I/O pin (Bank 1) |
| Pin 120 | I/O — User I/O pin (Bank 1) |
| Pin 121 | I/O — User I/O pin (Bank 1) |
| Pin 122 | GND — Ground |
| Pin 123 | I/O — User I/O pin (Bank 1) |
| Pin 124 | I/O — User I/O pin (Bank 1) |
| Pin 125 | I/O — User I/O pin (Bank 1) |
| Pin 126 | I/O — User I/O pin (Bank 1) |
| Pin 127 | I/O — User I/O pin (Bank 1) |
| Pin 128 | VCCINT — Core supply voltage (1.5 V) |
| Pin 129 | I/O — User I/O pin (Bank 1) |
| Pin 130 | I/O — User I/O pin (Bank 1) |
| Pin 131 | I/O — User I/O pin (Bank 1) |
| Pin 132 | GND — Ground |
| Pin 133 | I/O — User I/O pin (Bank 1) |
| Pin 134 | I/O — User I/O pin (Bank 1) |
| Pin 135 | I/O — User I/O pin (Bank 1) |
| Pin 136 | I/O — User I/O pin (Bank 1) |
| Pin 137 | I/O — User I/O pin (Bank 1) |
| Pin 138 | VCCIO1 — I/O Bank 1 supply voltage |
| Pin 139 | I/O — User I/O pin (Bank 1) |
| Pin 140 | I/O — User I/O pin (Bank 1) |
| Pin 141 | I/O — User I/O pin (Bank 1) |
| Pin 142 | I/O — User I/O pin (Bank 1) |
| Pin 143 | I/O — User I/O pin (Bank 1) |
| Pin 144 | GND — Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1C6T144C8N is suitable for 6 applications: Industrial Motor Control, Telecommunications Line Cards and Protocol Bridges, Legacy Glue-Logic and ASIC Replacement, Education and FPGA Training Platforms, Low-Cost Video Processing Pipelines, Data Acquisition Front-Ends.
Industrial Motor Control
The EP1C6T144C8N fits industrial motor-control boards because its 5,980 logic elements, 2 PLLs, and 92 Kbits of embedded RAM provide enough capacity to host encoder decoding (QEP), PWM generation, and current-loop state machines in a single chip. The 98 user I/Os comfortably connect to multi-axis power-stage gate drivers, Hall sensors, and isolated communication transceivers. The Cyclone I 0.13 µm process keeps static power low, an important factor in always-on factory cabinets.
Recommended
Telecommunications Line Cards and Protocol Bridges
In telecom line-interface cards, the EP1C6T144C8N serves as a low-cost protocol-bridging FPGA, mapping between legacy T1/E1 framers, I²S audio buses, and Ethernet MII/RMII PHYs. Its 275 MHz core plus 2 PLLs can drive 100 Mbps MII comfortably, while the 98 I/Os handle multiple serial streams with hardware-accelerated framing. The commercial 0°C to +85°C range suits controlled-environment central-office deployments where industrial-grade parts are unnecessary.
Recommended
Legacy Glue-Logic and ASIC Replacement
The EP1C6T144C8N is a workhorse replacement for aging 144-TQFP ASICs and discrete 74-series glue logic in long-life industrial platforms. Its SRAM-based configuration lets engineers re-spin functionality in software without respinning the silicon, dramatically reducing sustaining-engineering cost. The Cyclone I family's decade-long production history and Quartus II Web Edition free toolchain support mean designs can be maintained without expensive software licenses.
Recommended
Education and FPGA Training Platforms
Universities and FPGA training labs favor the EP1C6T144C8N because its 5,980 logic elements are large enough to host a Nios II soft processor and meaningful student projects, yet small enough that Quartus II Web Edition (free) can compile bitstreams within minutes. The 144-TQFP package is breadboard-friendly with 0.5 mm pitch adaptors, and the abundant EP1C6 development kit reference designs accelerate student onboarding. Long product-life assurance also lets universities stock lab kits with confidence.
Recommended
Low-Cost Video Processing Pipelines
The EP1C6T144C8N supports entry-level video processing such as NTSC/PAL decoding, on-screen-display overlay, and color-space conversion in cost-sensitive consumer equipment. Its 98 I/Os accommodate parallel ITU-R BT.601 video buses plus control peripherals, and the 92 Kbits of block RAM buffer line-store memory without external SRAM. The 1.5 V core with 3.3 V-tolerant I/Os makes it easy to interface directly to legacy video ADCs and DACs.
Recommended
Data Acquisition Front-Ends
The EP1C6T144C8N is a strong fit for multi-channel data-acquisition front-ends where it manages timing-critical ADC/DAC handshake logic, FIR filter pre-processing, and DMA transfers to a host MCU. The 2 PLLs generate multiple simultaneous sample clocks, while 92 Kbits of block RAM implement per-channel ping-pong buffers. The commercial temperature range suits benchtop and laboratory instruments, and the same PCB can host the EP1C6T144I7N industrial variant for field-deployed units.
Recommended
Recommended Products Summary
Engineering reference data for EP1C6T144C8N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1C6T144C7N | EP1C6T144C6N | EP1C6T144I7N | EP1C3T144C8N | EP1C6T144C8 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 144-TQFP | 144-TQFP - same | 144-TQFP - same | 144-TQFP - same | 144-TQFP - same | 144-TQFP - same |
| Logic Elements | 5,980 | 5,980 | 5,980 | 5,980 | 3,000 | 5,980 |
| Speed Grade | C8 (commercial) | C7 (faster) | C6 (fastest) | C7 (industrial) | C8 (commercial) | C8 (commercial) |
| Operating Temperature | 0°C to +85°C | 0°C to +85°C | 0°C to +85°C | -40°C to +100°C | 0°C to +85°C | 0°C to +85°C |
| User I/O Pins | 98 | 98 | 98 | 98 | 104 | 98 |
| Embedded RAM Bits | 92,160 | 92,160 | 92,160 | 92,160 | 59,904 | 92,160 |
| RoHS / Lead-Free | RoHS, Pb-free (N suffix) | RoHS, Pb-free | RoHS, Pb-free | RoHS, Pb-free | RoHS, Pb-free | Non-RoHS (no N suffix) |
Key Differentiators
- Sweet-spot density between EP1C3 and EP1C12 in Cyclone I family (vs EP1C3T144C8N)
- Industrial-temperature drop-in available for harsh-environment designs (vs EP1C6T144I7N)
- Faster C6/C7 speed grades enable tighter timing margins (vs EP1C6T144C6N)
Design Notes
The EP1C6T144C8N requires a regulated 1.5 V VCCINT rail capable of supplying transient currents up to ~500 mA during configuration, plus four independent VCCIO rails (1.5 V / 1.8 V / 2.5 V / 3.3 V) for I/O banks. Decouple each VCCINT pin with a 0.1 µF X7R ceramic placed within 5 mm of the pin, and bulk-decouple each VCCIO bank with 10 µF tantalum plus 0.1 µF ceramic. The PLL analog supply (VCCA_PLL) should be filtered through a ferrite bead and decoupled with 10 µF + 0.1 µF to suppress jitter.
Route JTAG (TCK, TMS, TDI, TDO) as a daisy-chain with 22 Ω series-termination resistors near the driver; keep the chain stub length under 25 mm to preserve signal integrity. Place the EPCS configuration flash within 50 mm of the ASDO/nCSO/DATA pins and use a 4-layer PCB with continuous ground plane under the TQFP footprint. Leave a 2 mm copper keep-out around the TQFP body for inspection access, and flood unused I/O bank area with VCCIO for shielding.
Do not leave MSEL[2:0] floating; tie them through 10 kΩ resistors to the correct configuration-mode logic level (AS mode = 000, JTAG-only = 101). The CONF_DONE and nSTATUS pins are open-drain and require external 10 kΩ pull-ups to VCCIO. Avoid using the EP1C6T144C8N in new designs requiring >85°C ambient operation - select EP1C6T144I7N (industrial) instead. Configuration failures on first prototypes are most often due to missing VCCA_PLL decoupling or incorrect MSEL strapping.
Compliance Information
RoHS compliant (N suffix denotes lead-free finish). REACH compliant per manufacturer declaration. Not AEC-Q100 qualified - select EP1C6T144I7N (industrial grade) for harsh-environment applications. Halogen-free molding compound per JEDEC JS709.
