EP1C6T144I6N - Cyclone FPGA 5980 Cells 144-TQFP | Altera / Intel
MPN: EP1C6T144I6N ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.4 | $254.00 |
| 100 | $22.1 | $2,210.00 |
| 500 | $19.8 | $9,900.00 |
| 1,000 | $17.6 | $17,600.00 |
Drop-in alternatives for EP1C6T144I6N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EP1C6T144I6N Maximum Ratings & Electrical Characteristics
| Family | Cyclone (First Generation) |
| Logic Elements | 5,980 |
| Process Technology | 130 nm CMOS |
| Core Voltage | 1.5 V |
| Maximum Internal Frequency | 405.2 MHz |
| Package | 144-pin TQFP (TQFP-144) |
| User I/O Count | 100+ (depends on bank configuration) |
| Embedded Memory (M4K blocks) | 20 blocks, ~92 Kbits total |
| Phase-Locked Loops (PLLs) | 2 |
| Speed Grade | -6 |
| Operating Temperature Range | -40 C to +100 C (Industrial) |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, SSTL-II, LVDS |
| Configuration Modes | AS, PS, JTAG |
| Mounting Type | Surface Mount (TQFP) |
| Lead-Free / RoHS | Yes (per 'N' suffix) |
EP1C6T144I6N Pin Configuration
| Pin 1 | I/O — User I/O (bank 1) |
| Pin 2 | I/O — User I/O (bank 1) |
| Pin 3 | I/O — User I/O (bank 1) |
| Pin 4 | I/O — User I/O (bank 1) |
| Pin 5 | I/O — User I/O (bank 1) |
| Pin 6 | I/O — User I/O (bank 1) |
| Pin 7 | VCCIO1 — Bank 1 I/O supply |
| Pin 8 | I/O — User I/O (bank 1) |
| Pin 9 | I/O — User I/O (bank 1) |
| Pin 10 | I/O — User I/O (bank 1) |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O (bank 1) |
| Pin 13 | I/O — User I/O (bank 1) |
| Pin 14 | I/O — User I/O (bank 1) |
| Pin 15 | I/O — User I/O (bank 1) |
| Pin 16 | I/O — User I/O (bank 1) |
| Pin 17 | VCCIO1 — Bank 1 I/O supply |
| Pin 18 | I/O — User I/O (bank 1) |
| Pin 19 | I/O — User I/O (bank 1) |
| Pin 20 | I/O — User I/O (bank 1) |
| Pin 21 | I/O — User I/O (bank 1) |
| Pin 22 | GND — Ground |
| Pin 23 | I/O — User I/O (bank 2) |
| Pin 24 | I/O — User I/O (bank 2) |
| Pin 25 | I/O — User I/O (bank 2) |
| Pin 26 | I/O — User I/O (bank 2) |
| Pin 27 | I/O — User I/O (bank 2) |
| Pin 28 | I/O — User I/O (bank 2) |
| Pin 29 | VCCIO2 — Bank 2 I/O supply |
| Pin 30 | I/O — User I/O (bank 2) |
| Pin 31 | I/O — User I/O (bank 2) |
| Pin 32 | I/O — User I/O (bank 2) |
| Pin 33 | I/O — User I/O (bank 2) |
| Pin 34 | I/O — User I/O (bank 2) |
| Pin 35 | I/O — User I/O (bank 2) |
| Pin 36 | VCCIO2 — Bank 2 I/O supply |
| Pin 37 | I/O — User I/O (bank 2) |
| Pin 38 | I/O — User I/O (bank 2) |
| Pin 39 | I/O — User I/O (bank 2) |
| Pin 40 | GND — Ground |
| Pin 41 | I/O — User I/O (bank 3) |
| Pin 42 | I/O — User I/O (bank 3) |
| Pin 43 | I/O — User I/O (bank 3) |
| Pin 44 | I/O — User I/O (bank 3) |
| Pin 45 | I/O — User I/O (bank 3) |
| Pin 46 | I/O — User I/O (bank 3) |
| Pin 47 | VCCIO3 — Bank 3 I/O supply |
| Pin 48 | I/O — User I/O (bank 3) |
| Pin 49 | I/O — User I/O (bank 3) |
| Pin 50 | I/O — User I/O (bank 3) |
| Pin 51 | I/O — User I/O (bank 3) |
| Pin 52 | I/O — User I/O (bank 3) |
| Pin 53 | I/O — User I/O (bank 3) |
| Pin 54 | VCCIO3 — Bank 3 I/O supply |
| Pin 55 | I/O — User I/O (bank 3) |
| Pin 56 | I/O — User I/O (bank 3) |
| Pin 57 | I/O — User I/O (bank 3) |
| Pin 58 | GND — Ground |
| Pin 59 | I/O — User I/O (bank 4) |
| Pin 60 | I/O — User I/O (bank 4) |
| Pin 61 | I/O — User I/O (bank 4) |
| Pin 62 | I/O — User I/O (bank 4) |
| Pin 63 | I/O — User I/O (bank 4) |
| Pin 64 | I/O — User I/O (bank 4) |
| Pin 65 | VCCIO4 — Bank 4 I/O supply |
| Pin 66 | I/O — User I/O (bank 4) |
| Pin 67 | I/O — User I/O (bank 4) |
| Pin 68 | I/O — User I/O (bank 4) |
| Pin 69 | I/O — User I/O (bank 4) |
| Pin 70 | I/O — User I/O (bank 4) |
| Pin 71 | I/O — User I/O (bank 4) |
| Pin 72 | VCCIO4 — Bank 4 I/O supply |
| Pin 73 | I/O — User I/O (bank 4) |
| Pin 74 | I/O — User I/O (bank 4) |
| Pin 75 | I/O — User I/O (bank 4) |
| Pin 76 | GND — Ground |
| Pin 77 | VCCINT — 1.5V core supply |
| Pin 78 | VCCINT — 1.5V core supply |
| Pin 79 | I/O — User I/O (bank 4) |
| Pin 80 | I/O — User I/O (bank 4) |
| Pin 81 | I/O — User I/O (bank 4) |
| Pin 82 | I/O — User I/O (bank 4) |
| Pin 83 | I/O — User I/O (bank 4) |
| Pin 84 | I/O — User I/O (bank 4) |
| Pin 85 | VCCIO4 — Bank 4 I/O supply |
| Pin 86 | I/O — User I/O (bank 4) |
| Pin 87 | I/O — User I/O (bank 4) |
| Pin 88 | I/O — User I/O (bank 4) |
| Pin 89 | I/O — User I/O (bank 4) |
| Pin 90 | I/O — User I/O (bank 4) |
| Pin 91 | I/O — User I/O (bank 4) |
| Pin 92 | GND — Ground |
| Pin 93 | I/O — User I/O (bank 3) |
| Pin 94 | I/O — User I/O (bank 3) |
| Pin 95 | I/O — User I/O (bank 3) |
| Pin 96 | I/O — User I/O (bank 3) |
| Pin 97 | I/O — User I/O (bank 3) |
| Pin 98 | I/O — User I/O (bank 3) |
| Pin 99 | VCCIO3 — Bank 3 I/O supply |
| Pin 100 | I/O — User I/O (bank 3) |
| Pin 101 | I/O — User I/O (bank 3) |
| Pin 102 | I/O — User I/O (bank 3) |
| Pin 103 | I/O — User I/O (bank 3) |
| Pin 104 | I/O — User I/O (bank 3) |
| Pin 105 | I/O — User I/O (bank 3) |
| Pin 106 | VCCIO3 — Bank 3 I/O supply |
| Pin 107 | I/O — User I/O (bank 3) |
| Pin 108 | I/O — User I/O (bank 3) |
| Pin 109 | I/O — User I/O (bank 3) |
| Pin 110 | GND — Ground |
| Pin 111 | I/O — User I/O (bank 2) |
| Pin 112 | I/O — User I/O (bank 2) |
| Pin 113 | I/O — User I/O (bank 2) |
| Pin 114 | I/O — User I/O (bank 2) |
| Pin 115 | I/O — User I/O (bank 2) |
| Pin 116 | I/O — User I/O (bank 2) |
| Pin 117 | VCCIO2 — Bank 2 I/O supply |
| Pin 118 | I/O — User I/O (bank 2) |
| Pin 119 | I/O — User I/O (bank 2) |
| Pin 120 | I/O — User I/O (bank 2) |
| Pin 121 | I/O — User I/O (bank 2) |
| Pin 122 | I/O — User I/O (bank 2) |
| Pin 123 | I/O — User I/O (bank 2) |
| Pin 124 | VCCIO2 — Bank 2 I/O supply |
| Pin 125 | I/O — User I/O (bank 2) |
| Pin 126 | I/O — User I/O (bank 2) |
| Pin 127 | I/O — User I/O (bank 2) |
| Pin 128 | GND — Ground |
| Pin 129 | I/O — User I/O (bank 1) |
| Pin 130 | I/O — User I/O (bank 1) |
| Pin 131 | I/O — User I/O (bank 1) |
| Pin 132 | I/O — User I/O (bank 1) |
| Pin 133 | I/O — User I/O (bank 1) |
| Pin 134 | I/O — User I/O (bank 1) |
| Pin 135 | VCCIO1 — Bank 1 I/O supply |
| Pin 136 | I/O — User I/O (bank 1) |
| Pin 137 | I/O — User I/O (bank 1) |
| Pin 138 | I/O — User I/O (bank 1) |
| Pin 139 | I/O — User I/O (bank 1) |
| Pin 140 | I/O — User I/O (bank 1) |
| Pin 141 | I/O — User I/O (bank 1) |
| Pin 142 | VCCIO1 — Bank 1 I/O supply |
| Pin 143 | TDI — JTAG test data in |
| Pin 144 | TMS — JTAG test mode select |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1C6T144I6N is suitable for 6 applications: Industrial Control & PLC Logic, Motor Control Co-Processor, Communication Bridge & Protocol Aggregator, LED Video Wall Scan & Refresh Driver, Software-Defined Radio Front-End Controller, Education & Hobby Digital Design Platform.
Industrial Control & PLC Logic
The EP1C6T144I6N fits industrial control and small PLC designs because its industrial -40 C to +100 C temperature range handles factory-floor thermal swings, while 5,980 logic elements are enough for ladder-logic-equivalent state machines, PID loops, and PWM generators. The two on-chip PLLs synthesize precise servo and motor-drive clocks from a low-cost crystal, and the LVDS-capable I/O bank interfaces to noise-immune industrial sensor buses without external transceivers. Use it to consolidate discrete 74-series glue logic and replace aging CPLDs with more headroom.
Recommended
Motor Control Co-Processor
For multi-axis motor control co-processing, the EP1C6T144I6N delivers 5,980 logic elements capable of running several independent field-oriented-control (FOC) state machines in parallel, offloading the host MCU. Its 20 M4K memory blocks provide deterministic cycle buffers for current and speed feedback, and two PLLs generate the high-resolution PWM carrier and quadrature-encoder sample clocks. The 144-TQFP package exposes enough user I/O to drive 6-8 half-bridges via external gate drivers, with margin for encoder, Hall-sensor, and CAN-style feedback lines.
Recommended
Communication Bridge & Protocol Aggregator
The EP1C6T144I6N excels as a protocol-aggregation bridge that fans out UART, SPI, I2C, and parallel buses to a host processor, because its 100+ I/O pins map easily to multi-drop sensor arrays and the 5,980 logic elements implement hardware FIFOs and CRC engines without CPU intervention. LVDS I/O support enables robust differential signalling across noisy backplanes up to several metres, while the 405.2 MHz internal fabric sustains multi-megabit serial streams. Industrial temperature grade allows deployment in outdoor enclosures, rack-mounted base stations, and vehicle gateways.
Recommended
LED Video Wall Scan & Refresh Driver
For LED video walls the EP1C6T144I6N's M4K memory blocks act as dual-port line buffers holding scan data while the previous frame is being shifted out, while the 5,980 logic elements implement gamma correction, refresh scheduling, and brightness modulation in parallel. Up to 100 user I/O pins drive several high-speed shift-register chains of LEDs simultaneously, and the PLLs synthesize the precise pixel clock from any standard video reference. Industrial temperature grade allows the controller to live inside the display cabinet without active cooling.
Recommended
Software-Defined Radio Front-End Controller
The EP1C6T144I6N is well-matched to SDR front-end controllers because its 5,980 logic elements implement CIC and FIR decimation filters, gain control loops, and IQ imbalance correction at baseband sample rates up to 80-100 MSPS. Two PLLs generate the ADC sampling clock and a phase-aligned LO offset, while LVDS pairs deliver parallel ADC data into the fabric without skew. The 144-TQFP footprint is hand-solderable on 4-layer prototype boards, accelerating experimental radio design cycles.
Recommended
Education & Hobby Digital Design Platform
The EP1C6T144I6N is ideal for university and hobbyist digital design courses because the 144-pin TQFP at 0.5 mm pitch is friendlier than BGA for hand-soldering and rework, while the 5,980 logic elements fit typical class projects (RISC CPUs, graphics pipelines, signal processors). It is fully supported by the free Quartus II / Quartus Prime Web Edition toolchain, enabling students to learn VHDL/Verilog without licence cost. Industrial temperature tolerance and lead-free assembly mean lab boards survive handling and reflow practice.
Recommended
Recommended Products Summary
Engineering reference data for EP1C6T144I6N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1C6T144C6N | EP1C6T144C7N | EP1C6T144C8N | EP1C6T144C6 | EP1C6T144C7 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Package | TQFP-144 | TQFP-144 (same) | TQFP-144 (same) | TQFP-144 (same) | TQFP-144 (same) | TQFP-144 (same) |
| Logic Elements | 5,980 | 5,980 | 5,980 | 5,980 | 5,980 | 5,980 |
| Temperature Range | -40 C to +100 C (Industrial) | 0 C to +85 C (Commercial) | 0 C to +85 C (Commercial) | 0 C to +85 C (Commercial) | 0 C to +85 C (Commercial) | 0 C to +85 C (Commercial) |
| Speed Grade | -6 | -6 (same) | -7 (faster) | -8 (fastest) | -6 (same) | -7 (faster) |
| Lead-Free / RoHS | Yes ('N' suffix) | Yes ('N' suffix) | Yes ('N' suffix) | Yes ('N' suffix) | No (no 'N' suffix) | No (no 'N' suffix) |
| Core Voltage | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V |
| Lifecycle Status | Last-Time-Buy | Last-Time-Buy | Last-Time-Buy | Last-Time-Buy | Obsolete | Obsolete |
| Approximate Unit Price (qty 1) | USD 28.50 | USD 18-22 (broker) | USD 20-25 (broker) | USD 22-28 (broker) | USD 5-10 (surplus) | USD 5-10 (surplus) |
Key Differentiators
- Industrial -40 C to +100 C temperature grade (vs EP1C6T144C6N)
- -6 speed grade (slower but cheapest, best for power-sensitive designs) (vs EP1C6T144C8N)
- RoHS-compliant lead-free assembly ('N' suffix) (vs EP1C6T144C6)
Design Notes
Estimated power budget for a 50%-utilization Cyclone design at 100 MHz: roughly 0.5-1.0 W from VCCINT (1.5V) plus I/O current of 10-20 mA per bank at 3.3V LVTTL. Place one 0.1 uF ceramic decoupling cap adjacent to every VCCINT, VCCIO, and PLL analog supply pin, and add two to four 47-100 uF bulk aluminium-polymer or tantalum capacitors near the package. Power-on sequence: VCCINT must reach 1.5V before VCCIO banks to avoid I/O latch-up; use a supervisor IC or sequenced LDO pair. Estimated input current at 1.5V x 0.6 A = 0.9 W typical.
Route JTAG (TCK, TMS, TDI, TDO) and configuration pins (MSEL, nCE, nCONFIG, nSTATUS, CONF_DONE) as short, parallel traces no longer than 50 mm to avoid signal-integrity issues; add 4.7 kohm pull-ups on nCE, nCONFIG, and CONF_DONE to VCCIO. Keep differential pair (LVDS) lengths matched within 0.5 mm. Provide a 4-layer stack-up with continuous ground plane under the TQFP-144 footprint and stitch vias every 5 mm along the perimeter. The TQFP-144 thermal pad (exposed pad, if present in the package variant) must be soldered to a ground-copper pour 10-10 mm minimum for heat spreading.
Do not leave configuration mode pins MSEL floating - tie them high or low to select AS (active serial, MSEL[2:0]=000), PS (passive serial, MSEL[2:0]=100), or JTAG-only (MSEL[2:0]=101) configuration. The nCONFIG pin must see a clean rising edge at power-up or the device will not configure; debounce any mechanical reset pushbutton with a 100 nF cap. Mixing 3.3V and 1.5V on the same I/O bank is illegal - group pins by voltage into the four VCCIO banks before PCB layout.
Compliance Information
RoHS-compliant per the 'N' suffix in the part number. Not AEC-Q100 qualified; the device is classified for industrial (not automotive) use. Halogen-free status not stated in the provided web data.
