EP1C6T144I7N - Cyclone FPGA, 5,980 LEs, 144-LQFP | Intel
MPN: EP1C6T144I7N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $66.2 | $66.20 |
| 10 | $59.5 | $595.00 |
| 100 | $53.2 | $5,320.00 |
| 500 | $47.8 | $23,900.00 |
| 1,000 | $42.5 | $42,500.00 |
Drop-in alternatives for EP1C6T144I7N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EP1C6T144I7N Maximum Ratings & Electrical Characteristics
| Series | Cyclone |
| Family | Cyclone (1st generation) |
| Logic Elements | 5,980 |
| Logic Array Blocks (LABs) | 598 |
| Total RAM Bits | 92,160 |
| Embedded RAM Blocks | 20 x M4K (4 Kbit each) |
| PLLs | 2 |
| User I/O Pins | 98 |
| I/O Banks | 4 |
| Core Voltage | 1.5 V |
| I/O Voltage | 1.5 V to 3.3 V |
| Maximum LVDS Pairs | 64 |
| Package | 144-LQFP (TQFP-144) |
| Operating Temperature | -40 °C to +100 °C |
| Speed Grade | I7 (industrial, slowest) |
| Mounting Type | Surface Mount |
| Process Technology | 0.13 μm SRAM |
| Configuration Modes | AS, PS, JTAG |
| RoHS Status | Compliant |
| MSL Level | 3 (168 hours) |
EP1C6T144I7N Pin Configuration
| Pin 1 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 2 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 3 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 4 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 5 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 6 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 7 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 8 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 9 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 10 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 11 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 12 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 13 | VCCINT — Core voltage supply (1.5 V) |
| Pin 14 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 15 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 16 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 17 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 18 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 19 | GND — Ground |
| Pin 20 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 21 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 22 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 23 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 24 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 25 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 26 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 27 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 28 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 29 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 30 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 31 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 32 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 33 | VCCINT — Core voltage supply (1.5 V) |
| Pin 34 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 35 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 36 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 37 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 38 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 39 | GND — Ground |
| Pin 40 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 41 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 42 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 43 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 44 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 45 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 46 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 47 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 48 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 49 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 50 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 51 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 52 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 53 | VCCINT — Core voltage supply (1.5 V) |
| Pin 54 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 55 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 56 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 57 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 58 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 59 | GND — Ground |
| Pin 60 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 61 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 62 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 63 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 64 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 65 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 66 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 67 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 68 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 69 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 70 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 71 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 72 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 73 | VCCINT — Core voltage supply (1.5 V) |
| Pin 74 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 75 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 76 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 77 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 78 | I/O — General-purpose user I/O pin (Bank 4) |
| Pin 79 | GND — Ground |
| Pin 80 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 81 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 82 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 83 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 84 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 85 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 86 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 87 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 88 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 89 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 90 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 91 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 92 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 93 | VCCINT — Core voltage supply (1.5 V) |
| Pin 94 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 95 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 96 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 97 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 98 | I/O — General-purpose user I/O pin (Bank 1) |
| Pin 99 | GND — Ground |
| Pin 100 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 101 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 102 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 103 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 104 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 105 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 106 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 107 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 108 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 109 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 110 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 111 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 112 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 113 | VCCINT — Core voltage supply (1.5 V) |
| Pin 114 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 115 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 116 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 117 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 118 | I/O — General-purpose user I/O pin (Bank 2) |
| Pin 119 | GND — Ground |
| Pin 120 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 121 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 122 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 123 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 124 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 125 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 126 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 127 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 128 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 129 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 130 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 131 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 132 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 133 | VCCINT — Core voltage supply (1.5 V) |
| Pin 134 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 135 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 136 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 137 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 138 | I/O — General-purpose user I/O pin (Bank 3) |
| Pin 139 | GND — Ground |
| Pin 140 | TMS — JTAG Test Mode Select |
| Pin 141 | TCK — JTAG Test Clock |
| Pin 142 | TDO — JTAG Test Data Out |
| Pin 143 | TDI — JTAG Test Data In |
| Pin 144 | nCONFIG — Configuration control (active-low reset) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1C6T144I7N is suitable for 6 applications: Industrial Control and Machine Interfaces, Digital Signal Processing Front-Ends, Video Bridging and Image Processing, Communication Protocol Bridging, Automotive Infotainment and Body Electronics, Glue-Logic Replacement in Legacy Systems.
Industrial Control and Machine Interfaces
The EP1C6T144I7N fits industrial control applications because of its -40 °C to +100 °C industrial temperature range, 98 user I/Os for sensor and actuator interfacing, and 5,980 LEs sufficient for state-machine and protocol-bridging logic. Its 2 PLLs support multi-clock domains common in motor-control loops, and the 144-LQFP package is hand-solderable for prototyping. The device replaces discrete glue logic in PLCs, HMI panels, and motor drives. Compared to a microcontroller, it offers deterministic parallel processing for hard-real-time control loops where deterministic latency matters more than sequential code execution.
Recommended
Digital Signal Processing Front-Ends
The EP1C6T144I7N suits DSP front-end tasks such as digital filtering, FFT pre-processing, and sample-rate conversion where parallel logic is faster than a sequential DSP chip. With 20 M4K RAM blocks totaling 92 Kbits, it provides on-chip data buffering for streaming audio or video samples. The 2 PLLs generate multiple sample-rate clocks from a single reference, and 98 I/Os support parallel ADC/DAC interfaces. Engineers typically use it in sonar pre-processors, audio codec bridges, and ultrasonic ranging systems.
Recommended
Video Bridging and Image Processing
The EP1C6T144I7N handles video-format bridging between cameras, displays, and processors. Its 64 LVDS pairs enable direct connection to flat-panel display interfaces and high-speed image sensors, while the 92 Kbits of block RAM serve as line buffers for video scaling and color-space conversion. With 5,980 LEs, designs can implement deinterlacers, scalers, and chroma-key overlays in a single chip. The industrial temperature rating suits outdoor kiosks and digital signage.
Recommended
Communication Protocol Bridging
The EP1C6T144I7N acts as a multi-protocol bridge between UART, SPI, I2C, CAN, and parallel buses in industrial and embedded networks. Its 5,980 LEs support simultaneous operation of several protocol engines without timing collisions, while 92 Kbits of block RAM buffer packet payloads. The 2 PLLs regenerate clocks for each downstream interface, and 98 user I/Os accommodate multiple connectors. Typical use cases include UART-to-SPI bridges, CAN gateways, and legacy-to-modern bus converters.
Recommended
Automotive Infotainment and Body Electronics
Although not AEC-Q100 qualified, the EP1C6T144I7N's industrial temperature range allows it to serve non-safety-critical automotive applications such as infotainment head-units, instrument clusters, and body controllers in non-safety roles. Its 64 LVDS pairs drive automotive LCD panels, and 5,980 LEs implement audio routing, CAN/LIN bridging, and graphic overlays. The 144-LQFP package handles the mechanical shock and vibration of vehicle environments. For safety-critical ADAS or chassis systems, an AEC-Q100 part is required.
Recommended
Glue-Logic Replacement in Legacy Systems
The EP1C6T144I7N is widely used to replace discrete 74-series logic chips, PALs, and GALs in legacy equipment where a hardware redesign is impractical. A single FPGA replaces dozens of small logic ICs, reducing board area and power consumption while adding reprogrammability for late-stage design changes. Its 98 user I/Os and 5,980 LEs accommodate most glue-logic retrofits, and the 144-LQFP footprint allows mechanical drop-in on legacy through-hole adapter boards. Engineers use it to extend product life without PCB respins.
Recommended
Recommended Products Summary
Engineering reference data for EP1C6T144I7N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1C6T144C8N | EP1C6T144I8N | EP1C6T144I7 | EP1C6T144I6N | EP1C6T144C7N | EP1C6T144C6N |
|---|---|---|---|---|---|---|---|
| Package | TQFP-144 (22x22 mm) | TQFP-144 (same) | TQFP-144 (same) | TQFP-144 (same) | TQFP-144 (same) | TQFP-144 (same) | TQFP-144 (same) |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 5,980 | 5,980 | 5,980 | 5,980 | 5,980 | 5,980 | 5,980 |
| Speed Grade | I7 (industrial, slowest) | C8 (commercial, fastest) | I8 (industrial, faster) | I7 (industrial, same) | I6 (industrial, slower) | C7 (commercial) | C6 (commercial, slowest) |
| Operating Temperature | -40 °C to +100 °C (industrial) | 0 °C to +85 °C (commercial) | -40 °C to +100 °C (industrial) | -40 °C to +100 °C (industrial) | -40 °C to +100 °C (industrial) | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) |
| Total RAM Bits | 92,160 | 92,160 | 92,160 | 92,160 | 92,160 | 92,160 | 92,160 |
| User I/Os | 98 | 98 | 98 | 98 | 98 | 98 | 98 |
| Core Voltage | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industrial temperature range with slowest speed grade for power-optimized designs (vs EP1C6T144C8N)
- Lower-cost option with same silicon as C7 grade (vs EP1C6T144C7N)
- Compact TQFP-144 footprint for hand-solderable prototyping (vs EP1C6Q240I7N)
Design Notes
The EP1C6T144I7N requires three power rails: 1.5 V VCCINT for the core logic, 1.5 V to 3.3 V VCCIO for the I/O banks (set per bank), and 3.3 V VCCPD for configuration/pre-charge. Decoupling requires at least eight 0.1 µF ceramic capacitors placed within 5 mm of the VCCINT pins, plus bulk capacitors (47 µF to 100 µF tantalum or polymer) on each rail. During configuration, VCCINT must ramp monotonically from 0 V to 1.5 V within 100 ms; failure to meet this can corrupt the configuration bitstream. Estimated: core current draw at 200 MHz internal operation with typical utilization (~30% LEs) is around 100 mA, peaking near 250 mA for full-utilization designs.
Route all four PLL power pins (VCC_PLL1, VCC_PLL2, GNDA_PLL1, GNDA_PLL2) with dedicated analog ground and power islands. Place 0.1 µF and 10 µF decoupling within 3 mm of each PLL pin to minimize jitter. For LVDS differential pairs, maintain 100 Ω differential impedance and match lengths within 0.5 mm. The 144-LQFP package has a 0.5 mm pitch and benefits from 4-layer PCBs with continuous ground and power planes under the device.
The I7 speed grade is the slowest industrial option and may fail timing closure for designs that compile cleanly at C8 commercial grade. Always benchmark the timing-critical path with the Quartus TimeQuest analyzer at the I7 grade before committing to layout. Another common pitfall is mixing VCCIO standards across banks without verifying bank-voltage conflicts - mixing 3.3 V LVCMOS and 2.5 V SSTL in adjacent banks requires per-bank voltage regulators. Finally, the device is now obsolete; long-term production designs should migrate to the Cyclone IV E family (EP4CE6E144) for active lifecycle support.
Compliance Information
RoHS compliant per Intel/Altera product page. Not AEC-Q100 qualified - do not use in safety-critical automotive systems.
