EP1C6T144C6 - Cyclone FPGA, 5,980 LEs, 144-LQFP | Intel / Altera
MPN: EP1C6T144C6 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.2 | $252.00 |
| 100 | $21.8 | $2,180.00 |
| 500 | $18.9 | $9,450.00 |
| 1,000 | $16.4 | $16,400.00 |
Drop-in alternatives for EP1C6T144C6 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP1C6T144C7N
✅ Drop-In✓ In Stock
$18.4 / Unit
View Datasheet →EP1C6T144C8N
✅ Drop-In✓ In Stock
$12.95 / Unit
View Datasheet →EP1C6T144I7N
✅ Drop-In✓ In Stock
$42.5 / Unit
View Datasheet →EP1C3T144C6
✅ Drop-In✓ In Stock
$17.32 / Unit
View Datasheet →EP1C6T144C6 Maximum Ratings & Electrical Characteristics
| Family | Cyclone I |
| Logic Elements | 5,980 |
| Logic Array Blocks (LABs) | 598 |
| Embedded Memory (RAM bits) | 92,160 |
| Maximum User I/O Pins | 98 |
| PLLs | 2 |
| Process Technology | 130 nm CMOS |
| Core Supply Voltage (VCCINT) | 1.5 V |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) |
| Maximum Internal Frequency | 405 MHz |
| Package | 144-LQFP (TQFP-144), 22 x 22 mm, 0.5 mm pitch |
| Operating Temperature Grade | Commercial (0 °C to +85 °C), inferred from 'C' speed-grade suffix |
| Speed Grade | 6 (slowest of the three Cyclone I grades: 6 / 7 / 8) |
| Mounting Type | Surface Mount |
| Configuration Method | JTAG / EPC serial configuration device |
| Supported I/O Standards | LVTTL, LVCMOS, SSTL, PCI, LVDS |
| RoHS Status | Compliant (lead-free TQFP package) |
EP1C6T144C6 Pin Configuration
| Pin 1 | I/O — User I/O pin (bank 1) |
| Pin 2 | I/O — User I/O pin (bank 1) |
| Pin 3 | I/O — User I/O pin (bank 1) |
| Pin 4 | I/O — User I/O pin (bank 1) |
| Pin 5 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 6 | I/O — User I/O pin (bank 1) |
| Pin 7 | I/O — User I/O pin (bank 1) |
| Pin 8 | I/O — User I/O pin (bank 1) |
| Pin 9 | I/O — User I/O pin (bank 1) |
| Pin 10 | GND — Ground |
| Pin 11 | I/O — User I/O pin (bank 1) |
| Pin 12 | I/O — User I/O pin (bank 1) |
| Pin 13 | I/O — User I/O pin (bank 1) |
| Pin 14 | TDI — JTAG Test Data Input |
| Pin 15 | TMS — JTAG Test Mode Select |
| Pin 16 | TCK — JTAG Test Clock |
| Pin 17 | I/O — User I/O pin (bank 1) |
| Pin 18 | I/O — User I/O pin (bank 1) |
| Pin 19 | I/O — User I/O pin (bank 1) |
| Pin 20 | I/O — User I/O pin (bank 1) |
| Pin 21 | I/O — User I/O pin (bank 1) |
| Pin 22 | I/O — User I/O pin (bank 1) |
| Pin 23 | VCCINT — Core supply voltage (1.5 V) |
| Pin 24 | I/O — User I/O pin (bank 1) |
| Pin 25 | I/O — User I/O pin (bank 1) |
| Pin 26 | I/O — User I/O pin (bank 1) |
| Pin 27 | I/O — User I/O pin (bank 1) |
| Pin 28 | I/O — User I/O pin (bank 1) |
| Pin 29 | GND — Ground |
| Pin 30 | I/O — User I/O pin (bank 1) |
| Pin 31 | I/O — User I/O pin (bank 1) |
| Pin 32 | I/O — User I/O pin (bank 1) |
| Pin 33 | I/O — User I/O pin (bank 1) |
| Pin 34 | I/O — User I/O pin (bank 1) |
| Pin 35 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 36 | I/O — User I/O pin (bank 1) |
| Pin 37 | CONF_DONE — Configuration done status (open-drain) |
| Pin 38 | nSTATUS — Configuration status (open-drain) |
| Pin 39 | DCLK — Configuration clock input |
| Pin 40 | nCONFIG — Configuration control (active-low) |
| Pin 41 | DATA0 — Configuration data input (bit 0) |
| Pin 42 | I/O — User I/O pin (bank 2) |
| Pin 43 | I/O — User I/O pin (bank 2) |
| Pin 44 | I/O — User I/O pin (bank 2) |
| Pin 45 | I/O — User I/O pin (bank 2) |
| Pin 46 | I/O — User I/O pin (bank 2) |
| Pin 47 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 48 | I/O — User I/O pin (bank 2) |
| Pin 49 | I/O — User I/O pin (bank 2) |
| Pin 50 | I/O — User I/O pin (bank 2) |
| Pin 51 | GND — Ground |
| Pin 52 | I/O — User I/O pin (bank 2) |
| Pin 53 | I/O — User I/O pin (bank 2) |
| Pin 54 | I/O — User I/O pin (bank 2) |
| Pin 55 | I/O — User I/O pin (bank 2) |
| Pin 56 | I/O — User I/O pin (bank 2) |
| Pin 57 | I/O — User I/O pin (bank 2) |
| Pin 58 | I/O — User I/O pin (bank 2) |
| Pin 59 | I/O — User I/O pin (bank 2) |
| Pin 60 | I/O — User I/O pin (bank 2) |
| Pin 61 | VCCINT — Core supply voltage (1.5 V) |
| Pin 62 | I/O — User I/O pin (bank 2) |
| Pin 63 | I/O — User I/O pin (bank 2) |
| Pin 64 | I/O — User I/O pin (bank 2) |
| Pin 65 | I/O — User I/O pin (bank 2) |
| Pin 66 | I/O — User I/O pin (bank 2) |
| Pin 67 | I/O — User I/O pin (bank 2) |
| Pin 68 | I/O — User I/O pin (bank 2) |
| Pin 69 | I/O — User I/O pin (bank 2) |
| Pin 70 | I/O — User I/O pin (bank 2) |
| Pin 71 | GND — Ground |
| Pin 72 | I/O — User I/O pin (bank 2) |
| Pin 73 | I/O — User I/O pin (bank 2) |
| Pin 74 | I/O — User I/O pin (bank 2) |
| Pin 75 | I/O — User I/O pin (bank 2) |
| Pin 76 | I/O — User I/O pin (bank 2) |
| Pin 77 | I/O — User I/O pin (bank 2) |
| Pin 78 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 79 | I/O — User I/O pin (bank 2) |
| Pin 80 | I/O — User I/O pin (bank 2) |
| Pin 81 | I/O — User I/O pin (bank 2) |
| Pin 82 | I/O — User I/O pin (bank 2) |
| Pin 83 | I/O — User I/O pin (bank 2) |
| Pin 84 | I/O — User I/O pin (bank 2) |
| Pin 85 | I/O — User I/O pin (bank 2) |
| Pin 86 | I/O — User I/O pin (bank 2) |
| Pin 87 | I/O — User I/O pin (bank 2) |
| Pin 88 | GND — Ground |
| Pin 89 | I/O — User I/O pin (bank 2) |
| Pin 90 | I/O — User I/O pin (bank 2) |
| Pin 91 | I/O — User I/O pin (bank 2) |
| Pin 92 | I/O — User I/O pin (bank 2) |
| Pin 93 | I/O — User I/O pin (bank 2) |
| Pin 94 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 95 | I/O — User I/O pin (bank 2) |
| Pin 96 | I/O — User I/O pin (bank 2) |
| Pin 97 | I/O — User I/O pin (bank 2) |
| Pin 98 | I/O — User I/O pin (bank 2) |
| Pin 99 | I/O — User I/O pin (bank 2) |
| Pin 100 | I/O — User I/O pin (bank 2) |
| Pin 101 | I/O — User I/O pin (bank 2) |
| Pin 102 | I/O — User I/O pin (bank 2) |
| Pin 103 | VCCINT — Core supply voltage (1.5 V) |
| Pin 104 | I/O — User I/O pin (bank 2) |
| Pin 105 | I/O — User I/O pin (bank 2) |
| Pin 106 | I/O — User I/O pin (bank 2) |
| Pin 107 | I/O — User I/O pin (bank 2) |
| Pin 108 | I/O — User I/O pin (bank 2) |
| Pin 109 | I/O — User I/O pin (bank 2) |
| Pin 110 | I/O — User I/O pin (bank 2) |
| Pin 111 | I/O — User I/O pin (bank 2) |
| Pin 112 | GND — Ground |
| Pin 113 | I/O — User I/O pin (bank 2) |
| Pin 114 | I/O — User I/O pin (bank 2) |
| Pin 115 | I/O — User I/O pin (bank 2) |
| Pin 116 | I/O — User I/O pin (bank 2) |
| Pin 117 | I/O — User I/O pin (bank 2) |
| Pin 118 | I/O — User I/O pin (bank 2) |
| Pin 119 | I/O — User I/O pin (bank 2) |
| Pin 120 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 121 | I/O — User I/O pin (bank 2) |
| Pin 122 | I/O — User I/O pin (bank 2) |
| Pin 123 | I/O — User I/O pin (bank 2) |
| Pin 124 | I/O — User I/O pin (bank 2) |
| Pin 125 | I/O — User I/O pin (bank 2) |
| Pin 126 | I/O — User I/O pin (bank 2) |
| Pin 127 | I/O — User I/O pin (bank 2) |
| Pin 128 | I/O — User I/O pin (bank 2) |
| Pin 129 | I/O — User I/O pin (bank 2) |
| Pin 130 | I/O — User I/O pin (bank 2) |
| Pin 131 | VCCINT — Core supply voltage (1.5 V) |
| Pin 132 | I/O — User I/O pin (bank 2) |
| Pin 133 | I/O — User I/O pin (bank 2) |
| Pin 134 | I/O — User I/O pin (bank 2) |
| Pin 135 | I/O — User I/O pin (bank 2) |
| Pin 136 | I/O — User I/O pin (bank 2) |
| Pin 137 | I/O — User I/O pin (bank 2) |
| Pin 138 | I/O — User I/O pin (bank 2) |
| Pin 139 | I/O — User I/O pin (bank 2) |
| Pin 140 | I/O — User I/O pin (bank 2) |
| Pin 141 | TDO — JTAG Test Data Output |
| Pin 142 | I/O — User I/O pin (bank 1) |
| Pin 143 | I/O — User I/O pin (bank 1) |
| Pin 144 | I/O — User I/O pin (bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1C6T144C6 is suitable for 6 applications: Industrial Control and Motor Drive Front-End, Consumer Electronics Glue Logic and Custom Interfaces, Video and Image Processing Pipeline, Communications Protocol Bridging, FPGA Prototyping and Educational Platforms, Test and Measurement Instrumentation Front-End.
Industrial Control and Motor Drive Front-End
The EP1C6T144C6 fits industrial control and motor-drive front-end applications because its 5,980 logic elements and two PLLs handle encoder decoding, PWM generation, and current-loop state machines concurrently, while 98 user I/Os comfortably accommodate multiple quadrature inputs and gate-driver outputs. Per the Cyclone I datasheet, the device supports 3.3 V LVTTL directly, allowing direct interfacing to 3.3 V gate drivers without level shifters. Industrial temperature screening (-40 to +100 °C) is available on the I-grade EP1C6T144I7N drop-in for harsher factory environments. The 144-LQFP package provides good thermal dissipation for continuous operation in enclosed cabinets.
Recommended
Consumer Electronics Glue Logic and Custom Interfaces
The EP1C6T144C6 is well suited for consumer glue logic because its 5,980 LEs can absorb a UART plus I2C plus SPI bridge, an LCD controller, and audio mux logic simultaneously without consuming external CPLDs. Per Altera's Cyclone I datasheet, the device's 1.5 V core plus multi-voltage VCCIO bank support enables direct 1.8 V, 2.5 V, and 3.3 V interface to application processors and peripherals. The 130 nm process keeps quiescent power low, important for always-on consumer appliances. Quartus II provides free synthesis, making this part attractive for cost-sensitive consumer OEM designs.
Recommended
Video and Image Processing Pipeline
The EP1C6T144C6 supports mid-resolution video processing pipelines where 5,980 LEs can implement a YUV-to-RGB color-space converter, a deinterlacer, and an OSD overlay in parallel. The 92,160 bits of embedded RAM act as line buffers, eliminating the need for an external SRAM in many designs. Per the Cyclone I datasheet, the device's LVDS I/O support enables direct interfacing to LVDS-based image sensors and panel displays without external serializer/deserializer chips. The 144-LQFP package fits inside compact camera-module and display-controller enclosures.
Recommended
Communications Protocol Bridging
The EP1C6T144C6 works as a protocol bridge converting between UART, SPI, I2C, I2S, and custom parallel buses in telecom and industrial networking gear. Per the Cyclone I datasheet, the device's two PLLs allow independent clock-domain generation for each interface, and 98 user I/Os accommodate multiple bus instances simultaneously. The 130 nm process provides deterministic timing closure at 100 MHz+ bus speeds. Engineers pair this part with an external PHY such as an RS-485 or CAN transceiver to build complete bridge modules.
Recommended
FPGA Prototyping and Educational Platforms
The EP1C6T144C6 is ideal for university FPGA labs and prototype boards because 5,980 LEs provide enough logic for a RISC-V soft-core, custom peripherals, and student projects without overflow. Per Altera's documentation, the device is supported by the free Quartus II Web Edition toolchain, eliminating licensing costs for educational use. The 144-LQFP package with 0.5 mm pitch is breadboard-friendly for breakout boards. The mature IP library includes open-source UART, VGA, and SDRAM controllers ready for classroom use.
Recommended
Test and Measurement Instrumentation Front-End
The EP1C6T144C6 fits test-and-measurement front-end designs because 5,980 LEs can implement custom trigger logic, waveform generation, and time-to-digital conversion in parallel with bus interfacing. Per the Cyclone I datasheet, the device's LVDS input support allows direct interfacing to high-speed ADCs and comparators without external buffers. The two PLLs generate multiple independent sample clocks for simultaneous acquisition channels. Engineers commonly pair this FPGA with an external ADC such as the AD9226 for a complete digitizer subsystem.
Recommended
Recommended Products Summary
Engineering reference data for EP1C6T144C6 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1C6T144C7N | EP1C6T144C8N | EP1C6T144I7N | EP1C3T144C6 |
|---|---|---|---|---|---|
| Package | 144-LQFP (TQFP-144), 22x22 mm, 0.5 mm pitch | 144-LQFP (TQFP-144) - same | 144-LQFP (TQFP-144) - same | 144-LQFP (TQFP-144) - same | 144-LQFP (TQFP-144) - same |
| Brand | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 5,980 | 5,980 | 5,980 | 5,980 | 3,000 |
| Speed Grade | 6 | 7 | 8 | 7 | 6 |
| Temperature Range | Commercial (0 to +85 °C) | Commercial (0 to +85 °C) | Commercial (0 to +85 °C) | Industrial (-40 to +100 °C) | Commercial (0 to +85 °C) |
| Embedded RAM | 92,160 bits | 92,160 bits | 92,160 bits | 92,160 bits | 59,904 bits |
| Max User I/O | 98 | 98 | 98 | 98 | 104 |
| Lead-Free (RoHS) | Yes (N-suffix variant) | Yes | Yes | Yes | Yes (N-suffix variant) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Speed-grade 6 (slowest) variant of the EP1C6T144 die in 144-LQFP (vs EP1C6T144C8N)
- Commercial temperature grade (0-85 °C) (vs EP1C6T144I7N)
- Same 144-LQFP footprint as EP1C3T144 (3,000 LEs) and EP1C12T144 (12,060 LEs) (vs EP1C3T144C6)
Design Notes
The EP1C6T144C6 requires three power rails: VCCINT (1.5 V core, ~100-300 mA depending on utilization), VCCIO1 and VCCIO2 (1.5/1.8/2.5/3.3 V per bank, each up to 200 mA). Place 0.1 µF and 10 µF decoupling capacitors within 5 mm of each supply pin. Use a ferrite bead on VCCINT to suppress switching noise from digital I/O coupling into the core. Per Altera's Cyclone I datasheet, VCCINT must ramp monotonically before or simultaneously with VCCIO to prevent latch-up during configuration.
Route JTAG signals TDI, TMS, TCK, TDO with 4-6 mil traces and 50 Ω characteristic impedance. Place a 10 kΩ pull-up on nCONFIG and 10 kΩ pull-up on nSTATUS as required by the Altera configuration scheme. Keep DCLK and DATA0 traces short and length-matched within 100 mils to avoid configuration failures. Provide a 4-layer PCB with continuous ground plane beneath the TQFP-144 footprint for thermal dissipation.
Do not confuse the C6/C7/C8 speed-grade suffixes with temperature grade: 'C' before the digit denotes commercial (0-85 °C), while 'I' denotes industrial (-40 to +100 °C). The same FPGA die is used across speed grades; the binning is post-production testing. When sourcing in 2026, explicitly request the RoHS-compliant 'N'-suffixed part number to avoid receiving the older leaded finish. Cyclone I devices require Quartus II 13.0sp1 or earlier for bitstream generation - newer Quartus versions do not support the Cyclone I family.
Compliance Information
Lead-free / RoHS-compliant when ordered with the 'N' suffix; the bare 'EP1C6T144C6' historically referred to a leaded variant. AEC-Q100 not applicable - this is a commercial/industrial FPGA. REACH SVHC compliance per Intel product declaration.
