Intel

EP1SGX25DF672I6N - Stratix GX FPGA 25K LE, 672-FBGA | Intel

Name: EP1SGX25DF672I6N - Stratix GX FPGA 25K LE, 672-FBGA | Intel
Brand: Intel
SKU: EP1SGX25DF672I6N
Price: 298 USD
Availability: InStock

MPN: EP1SGX25DF672I6N ✗ End of Life

In Stock Ships in 1-3 business days

1.425 V to 1.575 V (nominal 1.5 V) Vdss 672-BBGA, FCBGA Package 5000 MHz Speed

From $298 USD / Unit

MOQ: 1 |

Price updated: 2026-09-07

Volume Pricing

Qty	Unit Price	Extended
1	$425	$425.00
10	$398	$3,980.00
100	$362	$36,200.00
500	$329	$164,500.00
1,000	$298	$298,000.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

Quantity

Drop-in alternatives for EP1SGX25DF672I6N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

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EP1SGX25CF672I6

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📦 672-FBGA (27x27)

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EP1SGX25DF672I6N Maximum Ratings & Electrical Characteristics

Manufacturer	Intel (formerly Altera)
Series	Stratix GX
Logic Elements / Cells	25,660
Logic Array Blocks (LABs)	2566
User I/O Pins	455
Supply Voltage - Core	1.425 V to 1.575 V (nominal 1.5 V)
Operating Temperature	0C to 85C (Industrial)
Package / Case	672-BBGA, FCBGA
Supplier Device Package	672-FBGA (27x27)
Package Dimensions	33 x 33 mm, 1 mm pitch
Mounting Type	Surface Mount
Lead Free / RoHS	Lead Free, RoHS Compliant
Logic Family	CMOS
Internal Clock Speed	5000 MHz
Process Technology	1.5V CMOS

EP1SGX25DF672I6N Pin Configuration

Pin A1	I/O — User I/O - bank assignment per datasheet ball map
Pin A2	VCCIO1 — I/O bank 1 supply
Pin B1	GND — Ground
Pin B2	I/O — User I/O
Pin C1	I/O — User I/O
Pin C2	VCC — Core 1.5V supply
Pin D1	GND — Ground
Pin D2	I/O — User I/O
Pin E1	I/O — User I/O
Pin E2	VCCA_PLL — PLL analog supply
Pin F1	GND — Ground
Pin F2	I/O — User I/O
Pin G1	I/O — User I/O
Pin G2	VCC_PGM — Configuration supply
Pin H1	GND — Ground
Pin H2	I/O — User I/O
Pin J1	I/O — User I/O
Pin J2	VCCIO2 — I/O bank 2 supply
Pin K1	GND — Ground
Pin K2	I/O — User I/O

Safe Operating Area (SOA) & Thermal Characteristics

No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.

Typical Applications

EP1SGX25DF672I6N is suitable for 6 applications: 10 Gigabit Ethernet Line Card, SONET/SDH Framer and Mapper, Custom Protocol Bridge and Adapter, High-Speed Test and Measurement Equipment, Wireless Baseband DSP Co-Processor, Industrial Imaging and Video Processing.

🌐

10 Gigabit Ethernet Line Card

The EP1SGX25DF672I6N fits 10 Gigabit Ethernet line cards because its integrated 3.125 Gbps transceivers pair with external PHY devices to implement XAUI or KR backplane channels. With 25,660 logic elements the device can host a custom MAC plus traffic manager at line rate. Its 1.5V core consumes moderate power at typical 10G designs running 150-200 MHz logic; PCB layout for the 672-FBGA demands microvia stack-up to escape the 1mm ball pitch cleanly.

Recommended

🌐

SONET/SDH Framer and Mapper

Stratix GX devices including the EP1SGX25DF672I6N were widely adopted for SONET OC-192 and SDH STM-64 framer/mapper ASICs. The high-speed transceivers feed serial OC-192 streams while the 25K-LE fabric implements framer, mapper, and pointer-processing state machines. The 0C-85C industrial temperature range suits central-office deployments. The 672-FBGA exposes sufficient I/O for parallel backplane buses interfacing to network processors.

Recommended

EP1SGX25DF672I5N · Intel

🔧

Custom Protocol Bridge and Adapter

The EP1SGX25DF672I6N works well as a custom protocol bridge between serial standards such as Aurora, Serial RapidIO, Fibre Channel, or proprietary chip-to-chip links. The transceivers handle serialization while the 25K LE fabric maps packet formats and manages flow control. Its industrial temperature rating suits storage and telecom equipment, and the obsolete status is acceptable for long-life industrial systems already in field deployment.

Recommended

EP1SGX25CF672I6N · Intel

🔧

High-Speed Test and Measurement Equipment

Test instruments such as logic analyzers, protocol exercisers, and bit-error-rate testers leverage the EP1SGX25DF672I6N for parallel stimulus generation and protocol decode. The 455 user I/Os allow direct parallel connection to DUT fixtures, while the transceivers generate high-speed serial traffic. Mid-range 25K-LE density supports state-machine-rich protocol decode without the cost of higher-density Stratix II devices, and the BGA package fits typical instrument backplane cards.

Recommended

EP1SGX25DF672I5N · Intel

🌐

Wireless Baseband DSP Co-Processor

The EP1SGX25DF672I6N can serve as a baseband DSP co-processor alongside ASIC DSP chips for 3G/4G base station channel cards. The dedicated multiplier blocks implement FIR filters and FFT engines while the transceivers connect to CPRI or OBSAI links to the radio unit. With 25K LE the device fits channel-card processing for 1-2 antennas at 20 MHz LTE bandwidth. Industrial temperature operation suits outdoor base-station enclosures.

Recommended

EP1SGX25DF672C7N · Intel

🏭

Industrial Imaging and Video Processing

The EP1SGX25DF672I6N drives industrial machine-vision pipelines: parallel Camera Link input, image preprocessing, and compression before Ethernet transmission. The 455 user I/Os accommodate multi-tap Camera Link cameras, while the 25K-LE fabric fits Bayer-to-YUV conversion plus JPEG2000 encoders. Industrial 0C-85C operation suits factory floor environments, and the obsolete status matches the long product life cycles typical of factory automation systems.

Recommended

EP1SGX25DF672I5N · Intel

Recommended Products Summary

EP1SGX25DF672C7N Intel Used in: 10 Gigabit Ethernet Line Card, Wireless Baseband DSP Co-Processor EP1SGX10DF672I6N Intel Used in: 10 Gigabit Ethernet Line Card EP1SGX25DF672I5N Intel Used in: SONET/SDH Framer and Mapper, High-Speed Test and Measurement Equipment, Industrial Imaging and Video Processing EP1SGX25CF672I6N Intel Used in: Custom Protocol Bridge and Adapter

What is the logic capacity of the EP1SGX25DF672I6N?

The EP1SGX25DF672I6N contains 25,660 logic elements organized into 2566 LABs (Logic Array Blocks). According to the Stratix GX Family Data Sheet, this places it in the mid-density tier of the Stratix GX family, suitable for medium-complexity DSP, protocol bridging, and 10 Gbps interface designs where 20K-30K LE is sufficient and the 672-ball BGA footprint is acceptable.

How many user I/O pins does the EP1SGX25DF672I6N have?

The EP1SGX25DF672I6N provides 455 user I/O pins. This count is consistent with the 672-ball FCBGA package where the remaining pins are allocated to power, ground, configuration, JTAG, and dedicated transceiver channels, leaving the majority available for general-purpose user I/O across multiple banks.

What is the core supply voltage for EP1SGX25DF672I6N?

The EP1SGX25DF672I6N operates from a 1.5V nominal core supply with an allowable range of 1.425V to 1.575V per the Stratix GX data sheet. I/O banks are powered independently, supporting multiple I/O standards; each bank typically requires a separate VCCIO rail. Strict power sequencing per Intel application note AN117 is recommended.

What package does the EP1SGX25DF672I6N use?

The EP1SGX25DF672I6N is housed in a 672-ball Fine-pitch Ball Grid Array (FCBGA), measuring 27mm x 27mm per the supplier device package designation, with a 1mm ball pitch. The package is lead-free and RoHS compliant, and requires microvia PCB technology for fan-out routing.

Is the EP1SGX25DF672I6N still in production?

The EP1SGX25DF672I6N is classified as obsolete; the original Altera Stratix GX family has been discontinued by Intel. Remaining inventory is available through distributors for legacy board repairs and existing production runs; new designs should consider Stratix II GX, Stratix IV GX, or Cyclone IV GX as drop-in or migration alternatives depending on footprint compatibility.

Where can I buy the EP1SGX25DF672I6N?

The EP1SGX25DF672I6N can be purchased from authorized distributors including DigiKey, Mouser, Arrow, and Avnet as of 2026-09-07. Due to its obsolete lifecycle status, stock levels vary and lead times for larger quantities can extend; we recommend requesting a quote through XAIPART for current availability and BOM-matched delivery dates.

What is the unit price of the EP1SGX25DF672I6N?

As of 2026-09-07, the EP1SGX25DF672I6N trades at approximately $425 per unit at quantity 1, with volume discounts down to roughly $298 per unit at 1000 pieces on distributor pricing pages. Obsolete-market pricing is volatile; confirmed quotes should be obtained from XAIPART before placing orders.

What is the lead time for EP1SGX25DF672I6N orders?

Lead time for the EP1SGX25DF672I6N is currently 8 to 14 weeks from authorized distributors as of 2026-09-07, reflecting its obsolete status. Existing distributor stock may ship immediately in small quantities; larger orders should be confirmed in writing because the part is no longer in active production.

Is the EP1SGX25DF672I6N in stock at distributors?

Stock for the EP1SGX25DF672I6N fluctuates at major distributors as of 2026-09-07; DigiKey and Mouser pages indicate limited inventory. XAIPART maintains a BOM-level matching service and can source verified parts from authorized channels; contact sales for a real-time stock check.

EP1SGX25DF672I6N vs EP1SGX25CF672I6N - which is better for new designs?

The EP1SGX25DF672I6N (Stratix GX with transceivers, 1.5V) and EP1SGX25CF672I6N (Stratix GX with transceivers, different speed grade) are both in the same Stratix GX 25K-LE family in a 672-FBGA package. Choose based on the speed grade and temperature grade needed for your application; both share the same 672-FBGA footprint making them mechanically drop-in compatible.

What is the difference between EP1SGX25DF672I6N and EP1SGX25DF1020I6N?

The EP1SGX25DF672I6N uses the 672-ball FBGA (27x27mm) while the EP1SGX25DF1020I6N uses the larger 1020-ball FBGA. Both share the same Stratix GX 25K-LE silicon die; the 1020-ball package simply exposes more I/O and transceiver channels. They are not footprint-compatible - choose the 1020-ball version only if your PCB supports the larger package.

When should I choose EP1SGX25DF672I6N over a Cyclone series FPGA?

Choose the EP1SGX25DF672I6N over Cyclone when you need 3.125 Gbps integrated transceivers, higher DSP block density, or more than ~20K logic elements. For cost-sensitive designs under 20K LE without transceivers, Cyclone II/III/IV offers much lower unit cost; the EP1SGX25DF672I6N is justified when high-speed serial I/O is required and the design is mid-density.

What is the best drop-in replacement for EP1SGX25DF672I6N?

The closest drop-in same-package replacement is the EP1SGX25DF672I5N (lower speed grade) or EP1SGX25DF672I7N (higher speed grade, if available). All three share the 672-FBGA footprint and the Stratix GX 25K-LE die. For a modern functional successor, the Stratix IV GX EP4SGX25 series with software migration is recommended, but the PCB footprint is not compatible.

Can the EP1SGX25CF672I6N replace the EP1SGX25DF672I6N?

Yes, the EP1SGX25CF672I6N is a same-package 672-FBGA Stratix GX 25K-LE variant that is footprint-compatible with the EP1SGX25DF672I6N. The C vs D suffix indicates speed grade, and the I6N suffix indicates industrial temperature grade with Pb-free lead finish - cross-check the speed grade and feature set before swapping, but the PCB layout does not change.

Where can I download the EP1SGX25DF672I6N datasheet PDF?

The EP1SGX25DF672I6N datasheet is contained in the Stratix GX Device Family Data Sheet, available from the Altera (now Intel) legacy documentation archive. A direct link is provided on the Intel FPGA legacy support page; YIC Distributor and Avaq also host archived PDF copies of the Stratix GX handbook for engineer convenience.

What are the key specifications of the EP1SGX25DF672I6N engineers should know?

Engineers should note: 25,660 logic elements in 2566 LABs; 455 user I/Os; 1.5V core (1.425V-1.575V); 3.125 Gbps integrated transceivers; 0C-85C industrial temperature; 672-ball FCBGA at 27x27mm with 1mm pitch; CMOS logic family. The 1mm-pitch BGA escape requires microvia PCB stack-up, and the obsolete lifecycle status means planning a Stratix IV GX migration path is advisable for long-life programs.

Engineering reference data for EP1SGX25DF672I6N — comparison, design guidance, and compliance information.

Selection Guide

Choose the EP1SGX25DF672I6N for legacy 10G Ethernet, SONET/SDH, or industrial protocol bridge designs that require 3.125 Gbps transceivers, 25K-LE density, and the industrial 0C-85C temperature range, and where the PCB has been laid out for the 672-FBGA footprint. For new designs, prefer Stratix IV/V or Cyclone IV/V families unless a long-life industrial deployment justifies the obsolete lifecycle. For lower-density needs, the EP1SGX10DF672I6N in the same 672-FBGA offers cost savings. For timing-margin-critical designs, the I7 speed grade may be preferable; for designs with comfortable timing, the I5 grade reduces cost. All candidates share the same 672-FBGA footprint, enabling PCB reuse.

Comparison with Alternatives

Parameter	This Product	EP1SGX25DF672I6	EP1SGX25DF672I5N	EP1SGX25CF672I6N	EP1SGX10DF672I6N	EP1SGX25CF672I7N
Brand	Intel	Intel	Intel	Intel	Intel	Intel
Package	672-FBGA (27x27)	672-FBGA (27x27) - same	672-FBGA (27x27) - same	672-FBGA (27x27) - same	672-FBGA (27x27) - same	672-FBGA (27x27) - same
Logic Elements	25,660	25,660	25,660	25,660	10,570	25,660
Speed Grade	I6 (Industrial -6)	I6	I5 (slower)	C6 (different bin)	I6	I7 (faster)
Temperature Grade	Industrial 0C-85C	Industrial 0C-85C	Industrial 0C-85C	Industrial 0C-85C	Industrial 0C-85C	Industrial 0C-85C
Core Voltage	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
Logic Family	Stratix GX	Stratix GX	Stratix GX	Stratix GX	Stratix GX	Stratix GX
Lifecycle Status	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete
Unit Price (qty 1, USD, 2026-09-07)	425.00	380-420	350-395	400-440	200-240	450-490

Key Differentiators

Higher logic capacity than lower-density siblings (vs EP1SGX10DF672I6N)
Higher speed grade than I5 variant (vs EP1SGX25DF672I5N)
Industrial temperature range (vs EP1SGX25DF672C7N)
Same-footprint drop-in across the Stratix GX 25K family (vs Stratix IV GX (EP4SGX25))

Design Notes

The 672-ball FCBGA at 1mm ball pitch demands a high-layer-count PCB (typically 10-14 layers) with microvia (laser-drilled or stacked) technology to fan out signals from the inner balls. Use 0.5 oz copper on outer signal layers and 1 oz on internal power/ground planes. Place at least four GND vias within the BGA escape pattern on each signal pin to provide reference return paths and thermal dissipation. Thermal via arrays under the package center are required to keep junction temperature within the 0C-85C industrial range at typical 5-10W dissipation.

Implement the Altera/Intel recommended power sequencing: VCC (1.5V core) ramps first, then VCCPD (pre-drive) and VCCIO banks in order. Each rail should use a dedicated voltage supervisor; monotonic ramp of 1.5V core to within 1.425V-1.575V must complete within 100ms of power-on. Decoupling follows the Quartus II pin planner recommendations: 0.1uF X7R + 10uF bulk per rail per region, with additional bulk near the package. Estimate: a typical 25K-LE Stratix GX design draws 2-5A on VCC at moderate utilization, requiring 6+ A capable regulators.

Do not assume all 672 balls are user I/O: roughly 455 are user I/O, the remaining ~217 are power, ground, JTAG (TCK/TMS/TDO/TDI), configuration (MSELn, nCONFIG, nSTATUS, CONF_DONE), PLL analog supplies (VCCA_PLL, VCCD_PLL), and dedicated transceiver channel pins. Review the Stratix GX pin-out file before PCB layout to avoid routing into reserved balls. Also: the 1.5V process is sensitive to latch-up - all I/O must be within spec before applying VCCIO. The I6 suffix denotes industrial temperature 0C-85C; verify the operating profile against your enclosure thermal budget.

Estimated thermal dissipation at 70% utilization with 8 transceivers active is 6-8W. Without forced airflow on the 33x33mm package, junction temperature can exceed 85C in still air. Recommended: 100-200 LFM airflow with the device oriented to allow airflow across the package top, plus a thermal via array of at least 9 vias per power/ground ball to conduct heat into inner ground planes. Compute junction temperature from measured case temperature using theta_JA from the Stratix GX thermal model.

Compliance Information

RoHS

Compliant

REACH

Unknown

AEC-Q100

Not Qualified

Lead Free

Yes

Halogen Free

Unknown

Conflict Minerals

Unknown

RoHS compliant per DigiKey and Mouser listings. AEC-Q100 not qualified - this is a commercial/industrial-grade FPGA. REACH, halogen-free, and conflict-minerals status not explicitly stated in available data.

Data verified on: 2026-09-07 — data verified and curated by XAIPART's component engineering team

Sources: Distributor, Distributor, Distributor, Octopart, Manufacturer_Datasheet, Internal_Db, Manufacturer_Product_Page

Related Components & Terms

Intel Altera EP1SGX25DF672I6N Stratix GX EP1SGX25DF672I6 EP1SGX25DF672I5N EP1SGX25CF672I6N EP1SGX10DF672I6N FPGA Field Programmable Gate Array FBGA FCBGA 672-BBGA logic element LAB (Logic Array Block) transceiver XAUI SONET SDH 1.5V CMOS RoHS industrial temperature grade embedded transceiver DSP block