EP1SGX25CF672I6 - 25K LEs Stratix GX FPGA, 672-FBGA | Intel
MPN: EP1SGX25CF672I6 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $256.5 | $2,565.00 |
| 100 | $228 | $22,800.00 |
| 500 | $199.5 | $99,750.00 |
| 1,000 | $171 | $171,000.00 |
Drop-in alternatives for EP1SGX25CF672I6 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP1SGX25CF672I6N
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View Datasheet →EP1SGX25CF672C7N
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View Datasheet →EP1SGX25CF672C7
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View Datasheet →EP1SGX25CF672C6N
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View Datasheet →EP1SGX25CF672C6
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View Datasheet →EP1SGX25CF672C5
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View Datasheet →EP1SGX25-CF672-I6
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$168 / Unit
View Datasheet →EP1SGX25CF672I6 Maximum Ratings & Electrical Characteristics
| Family | Stratix GX |
| Logic Elements | 25,660 |
| Logic Array Blocks (LABs) | 2,566 |
| Total RAM Bits | 1,944,576 |
| User I/O Pins | 455 |
| Core Supply Voltage | 1.425 V to 1.575 V (1.5 V typical) |
| Process Technology | 130 nm CMOS |
| Internal Clock Performance | Up to 5000 MHz |
| Package | 672-ball FBGA (27 x 27 mm, 1 mm pitch) |
| Mounting Type | Surface Mount |
| Operating Junction Temperature | -40C to +100C |
| RoHS Status | Compliant (lead-free FBGA) |
| Lead-Free | Yes |
EP1SGX25CF672I6 672-ball fbga (27 x 27 mm, 1 mm pitch) Pin Configuration Guide
Complete pinout information for EP1SGX25CF672I6 (672-ball fbga (27 x 27 mm, 1 mm pitch) package) with 455 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1SGX25CF672I6.
Refer to the datasheet for full pin configuration.
Estimated pin count: 455 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1SGX25CF672I6 is suitable for 6 applications: Multi-Gigabit Serial Backplane Routing, Broadcast Video Editing Systems, Software-Defined Radio (SDR) Platforms, PCI Express Endpoint Cards, Telecom Line Card Aggregation, High-Speed Test and Measurement Instrumentation.
Multi-Gigabit Serial Backplane Routing
The EP1SGX25CF672I6 integrates up to twenty SERDES channels at data rates up to 3.125 Gbps per the Stratix GX handbook, enabling direct backplane serial links without external PHY chips. With 455 user I/O pins and 25,660 logic elements, the device can implement custom MAC-layer packet processing, link-state management, and aggregation logic alongside the serial I/O. Channel-bonding to standards such as SerialLite II, XAUI (4x3.125 Gbps), and PCI Express x4/x8 reduces board area and BOM cost in chassis-to-chassis interconnects.
Recommended
Broadcast Video Editing Systems
The EP1SGX25CF672I6's combination of 1.94 Mbit embedded RAM, 16 DSP blocks (per the Stratix GX handbook), and multi-gigabit serial transceivers suits uncompressed HD-SDI video routers and editing systems. The fabric performs real-time color-space conversion, frame-buffer management, and embedded audio de-embed/re-embed, while the SERDES links transport SDI streams to back-end storage. The 455 I/O count accommodates parallel video bus capture alongside serial I/O on the same device.
Recommended
Software-Defined Radio (SDR) Platforms
The EP1SGX25CF672I6 supports SDR waveform implementation through its DSP block array (224 GMACS performance per the Stratix GX handbook), high-speed ADC/DAC interfaces, and SERDES for digital RF data transport. The 25K logic elements implement channelization, FFT/iFFT engines, and modulation/demodulation algorithms, while SERDES links provide low-latency paths to RF front-end digitizers. Industrial temperature range (-40C to 100C) supports outdoor and military SDR installations.
Recommended
PCI Express Endpoint Cards
The EP1SGX25CF672I6's hard PCI Express IP core supports x1, x4, and x8 endpoint implementations at 2.5 Gbps per lane through the embedded SERDES, eliminating external PHY silicon. The 25,660 logic elements and 1.94 Mbit block RAM implement protocol stack, DMA engines, and application logic for add-in cards. The 672-FBGA package supports differential SERDES pairs plus 455 user I/O for external memory and connector interfaces, suitable for server and workstation add-in cards.
Recommended
Telecom Line Card Aggregation
Telecom line cards use the EP1SGX25CF672I6 to bond SERDES channels for SPI-3/SPI-4.2, RapidIO, and proprietary backplane links at gigabit rates per the Stratix GX handbook. The fabric implements TDM framer/deframer, packet classification, and traffic management with the on-chip DSP and block RAM. The 1.5V core, multi-rail I/O banks (LVTTL, LVCMOS, SSTL, HSTL, LVDS), and industrial temperature rating suit central-office deployments.
Recommended
High-Speed Test and Measurement Instrumentation
The EP1SGX25CF672I6 provides 455 I/O pins for parallel ADC/DAC interfacing and SERDES channels up to 3.125 Gbps for captured-data streaming to host processors, making it well suited for high-end oscilloscopes, logic analyzers, and protocol testers. The 25K logic elements implement real-time triggering, pattern generation, and on-device statistics, while the 1.94 Mbit block RAM serves as deep sample buffer memory. Industrial temperature rating supports lab and field-test environments.
Recommended
Recommended Products Summary
Engineering reference data for EP1SGX25CF672I6 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1SGX25CF672I6N | EP1SGX25CF672C7N | EP1SGX25CF672C7 | EP1SGX25CF672C6N | EP1SGX25CF672C6 | EP1SGX25CF672C5 | EP1SGX25-CF672-I6 |
|---|---|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 672-FBGA (CF672) | 672-FBGA (CF672) - same | 672-FBGA (CF672) - same | 672-FBGA (CF672) - same | 672-FBGA (CF672) - same | 672-FBGA (CF672) - same | 672-FBGA (CF672) - same | 672-FBGA (CF672) - same |
| Logic Elements | 25,660 | 25,660 | 25,660 | 25,660 | 25,660 | 25,660 | 25,660 | 25,660 |
| Total RAM Bits | 1,944,576 | 1,944,576 | 1,944,576 | 1,944,576 | 1,944,576 | 1,944,576 | 1,944,576 | 1,944,576 |
| User I/O | 455 | 455 | 455 | 455 | 455 | 455 | 455 | 455 |
| Temperature Grade | Industrial (-40C to 100C) | Industrial (-40C to 100C) | Commercial (0C to 85C) | Commercial (0C to 85C) | Commercial (0C to 85C) | Commercial (0C to 85C) | Commercial (0C to 85C) | Industrial (-40C to 100C) |
| Speed Grade | I6 (-6 speed, industrial) | I6 (-6) | C7 (-7) | C7 (-7) | C6 (-6) | C6 (-6) | C5 (-5, slowest) | I6 (-6) |
| Lead-Free (Pb-Free) | Yes (Pb-free FBGA) | Yes | Yes | No (leaded) | Yes | No (leaded) | No (leaded) | Yes |
Key Differentiators
- Lead-free / Pb-free ball finish required for RoHS-compliant designs (vs EP1SGX25CF672C7 (leaded ball finish))
- Industrial temperature grade for -40C to 100C operation (vs EP1SGX25CF672C7N (commercial 0C to 85C))
- I6 speed grade with -6 timing for high-performance designs (vs EP1SGX25CF672C5 (-5 speed, slowest))
- Full 25K LE density in the Stratix GX family (vs EP1SGX10CF672C7 (10K LE Stratix GX, same package))
Design Notes
The EP1SGX25CF672I6 requires multi-rail decoupling per the Stratix GX handbook. Place 0.1 uF and 0.01 uF X7R capacitors as close as possible to every VCC, VCCIO, VCCA_PLL, and VCCH pin. The PLL analog supply (VCCA_PLL) must be isolated from digital VCC by a ferrite bead and decoupled with a 10 uF tantalum in parallel with 0.1 uF ceramic. SERDES transceiver supplies (VCCH, VCCL) require their own low-noise LDOs (e.g., LT3027) to meet jitter specifications above 3 Gbps.
Estimated: at maximum toggle rate across all 25,660 LEs and active SERDES, the EP1SGX25CF672I6 dissipates approximately 5-8 W depending on logic utilization and transceiver channel count. With theta_JA of approximately 12-15 C/W on a 4-layer JEDEC test board, the junction temperature could rise 60-120 C above ambient. For industrial-grade deployments (junction 100 C max), forced-air airflow or a heatsink with thermal interface material is recommended when sustained logic utilization exceeds 60%.
Differential SERDES pair routing on the EP1SGX25CF672I6 must use 100 ohm differential impedance with matched length within 150 mils per the Stratix GX layout guidelines. Reference-clock routing to dedicated REFCLK pins must be isolated from digital switching signals and routed on inner stripline layers. Place the device on layer 2 with high-speed SERDES breaks to outer layers via stitched ground vias, and avoid routing digital signals directly under the BGA field to minimize crosstalk into the clock network.
Do not assume the EP1SGX25CF672I6 is pin-compatible with newer Stratix II/III/IV/V GX families - those use different die architectures and different BGA ballouts even when package code (F672) is similar. Always re-validate PCB footprint against the target device's package specifications before substitution. Also confirm JTAG chain and configuration scheme (PS, FPP, AS, JTAG) match the target board design, as configuration pin usage may differ between legacy Altera FPGA families.
Compliance Information
RoHS-compliant per Altera material declaration; lead-free FBGA ball finish (Pb-free). Industrial temperature grade is not AEC-Q100 qualified (automotive). For automotive applications, evaluate Cyclone IV/V automotive-grade devices instead.
