Altera

EPF8820ATC144-1 - FLEX 8000 FPGA, 672 Cells, 112 I/O, 144-TQFP | Altera

Name: EPF8820ATC144-1 - FLEX 8000 FPGA, 672 Cells, 112 I/O, 144-TQFP | Altera
Brand: Altera
SKU: EPF8820ATC144-1
Price: 15.95 USD
Availability: InStock

MPN: EPF8820ATC144-1 ✗ End of Life

In Stock Ships in 1-3 business days

5.0 V (MultiVolt I/O supports 3.3 V or 5.0 V) Vdss 144-pin TQFP Package -1 (slowest) Speed

From $15.95 USD / Unit

MOQ: 1 |

Price updated: 2026-09-11

Volume Pricing

Qty	Unit Price	Extended
1	$28.5	$28.50
10	$25.2	$252.00
100	$21.75	$2,175.00
500	$18.4	$9,200.00
1,000	$15.95	$15,950.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

Quantity

Drop-in alternatives for EPF8820ATC144-1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Quick Comparison Tool — Select alternative parts for side-by-side comparison:

EPF8820ATC144-4

✅ Drop-In

Intel

📦 144-pin TQFP

FLEX 8000 · 672 · 84 · 8000 · 112 · 8000 · 125 MHz · 0.42 µm CMOS SRAM

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$11.1 / Unit

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EPF8820ATC144-3

✅ Drop-In

Intel

📦 144-pin TQFP

FLEX 8000 · FLEX 8000 · 672 · 16,000 · 84 · up to 1,500 · 112 (per Mouser; DigiKey lists 152 for BGA variant) · 4.75 V to 5.25 V (5.0 V nominal)

✓ In Stock

$9.25 / Unit

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EPF8820ATC144-2

✅ Drop-In

Intel

📦 144-pin TQFP

FLEX 8000 · 672 · 8,000 · 84 · 112 · 144-LQFP (TQFP) · 0.42 um CMOS · 5 V

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EPF8820ATC144-4N

✅ Drop-In

Intel

📦 144-pin TQFP

FLEX 8000 · 8,000 · 672 · 84 · 112 · 8 · 0.42 µm CMOS · 5 V

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$15.2 / Unit

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EPF8820ATC144-3N

✅ Drop-In

Intel

📦 144-pin TQFP

FLEX 8000 · 672 · 8,000 (typical) · 84 · 112 to 152 (per package) · 0.42 µm CMOS SRAM · 4.75 V to 5.25 V (5 V nominal) · -3

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EPF8820ATC144-2N

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Altera

📦 144-pin TQFP

FLEX 8000 · 8,000 · 672 · 84 · 112 · 125 MHz · 0.42 µm CMOS · 5 V

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EPF8820ATC144-1 Maximum Ratings & Electrical Characteristics

Family	FLEX 8000
Device	EPF8820A
Logic Cells	672
Logic Array Blocks (LABs)	84
User I/Os	112
Equivalent Gates	~8,000 usable gates
Flip-Flops (max)	1,500
Supply Voltage	5.0 V (MultiVolt I/O supports 3.3 V or 5.0 V)
Process Technology	CMOS SRAM
Speed Grade	-1 (slowest)
Operating Temperature	0C to 70C (commercial)
Package	144-pin TQFP
Configuration Method	SRAM, loaded via EPC1 / EPC1064 / EPC1213 / EPC1441 or parallel EPROM
In-Circuit Reconfigurability	Yes (ICR)
JTAG Boundary Scan	Yes (IEEE 1149.1)

EPF8820ATC144-1 Pin Configuration

Pin 1	I/O — User I/O (bank A)
Pin 2	I/O — User I/O (bank A)
Pin 3	I/O — User I/O (bank A)
Pin 4	I/O — User I/O (bank A)
Pin 5	I/O — User I/O (bank A)
Pin 6	I/O — User I/O (bank A)
Pin 7	I/O — User I/O (bank A)
Pin 8	I/O — User I/O (bank A)
Pin 9	I/O — User I/O (bank A)
Pin 10	I/O — User I/O (bank A)
Pin 11	I/O — User I/O (bank A)
Pin 12	I/O — User I/O (bank A)
Pin 13	GND — Ground
Pin 14	I/O — User I/O (bank A)
Pin 15	I/O — User I/O (bank A)
Pin 16	I/O — User I/O (bank A)
Pin 17	I/O — User I/O (bank A)
Pin 18	I/O — User I/O (bank A)
Pin 19	I/O — User I/O (bank A)
Pin 20	I/O — User I/O (bank A)
Pin 21	I/O — User I/O (bank A)
Pin 22	I/O — User I/O (bank A)
Pin 23	I/O — User I/O (bank A)
Pin 24	I/O — User I/O (bank A)
Pin 25	I/O — User I/O (bank A)
Pin 26	I/O — User I/O (bank A)
Pin 27	I/O — User I/O (bank A)
Pin 28	I/O — User I/O (bank A)
Pin 29	I/O — User I/O (bank A)
Pin 30	I/O — User I/O (bank A)
Pin 31	I/O — User I/O (bank A)
Pin 32	I/O — User I/O (bank A)
Pin 33	VCCIO_A — I/O bank A supply (3.3V or 5.0V)
Pin 34	I/O — User I/O (bank A)
Pin 35	I/O — User I/O (bank A)
Pin 36	I/O — User I/O (bank A)
Pin 37	GND — Ground
Pin 38	I/O — User I/O (bank A)
Pin 39	I/O — User I/O (bank A)
Pin 40	I/O — User I/O (bank A)
Pin 41	I/O — User I/O (bank A)
Pin 42	I/O — User I/O (bank A)
Pin 43	I/O — User I/O (bank A)
Pin 44	I/O — User I/O (bank A)
Pin 45	I/O — User I/O (bank A)
Pin 46	I/O — User I/O (bank A)
Pin 47	I/O — User I/O (bank A)
Pin 48	I/O — User I/O (bank A)
Pin 49	I/O — User I/O (bank A)
Pin 50	I/O — User I/O (bank A)
Pin 51	I/O — User I/O (bank A)
Pin 52	I/O — User I/O (bank A)
Pin 53	I/O — User I/O (bank A)
Pin 54	I/O — User I/O (bank A)
Pin 55	I/O — User I/O (bank A)
Pin 56	I/O — User I/O (bank A)
Pin 57	I/O — User I/O (bank A)
Pin 58	I/O — User I/O (bank A)
Pin 59	I/O — User I/O (bank A)
Pin 60	I/O — User I/O (bank A)
Pin 61	I/O — User I/O (bank A)
Pin 62	I/O — User I/O (bank A)
Pin 63	I/O — User I/O (bank A)
Pin 64	I/O — User I/O (bank A)
Pin 65	I/O — User I/O (bank A)
Pin 66	I/O — User I/O (bank A)
Pin 67	I/O — User I/O (bank A)
Pin 68	I/O — User I/O (bank A)
Pin 69	I/O — User I/O (bank A)
Pin 70	I/O — User I/O (bank A)
Pin 71	I/O — User I/O (bank A)
Pin 72	I/O — User I/O (bank A)
Pin 73	VCCINT — Core supply (5.0V)
Pin 74	I/O — User I/O (bank B)
Pin 75	I/O — User I/O (bank B)
Pin 76	I/O — User I/O (bank B)
Pin 77	GND — Ground
Pin 78	I/O — User I/O (bank B)
Pin 79	I/O — User I/O (bank B)
Pin 80	I/O — User I/O (bank B)
Pin 81	I/O — User I/O (bank B)
Pin 82	I/O — User I/O (bank B)
Pin 83	I/O — User I/O (bank B)
Pin 84	I/O — User I/O (bank B)
Pin 85	I/O — User I/O (bank B)
Pin 86	I/O — User I/O (bank B)
Pin 87	I/O — User I/O (bank B)
Pin 88	I/O — User I/O (bank B)
Pin 89	I/O — User I/O (bank B)
Pin 90	I/O — User I/O (bank B)
Pin 91	I/O — User I/O (bank B)
Pin 92	I/O — User I/O (bank B)
Pin 93	I/O — User I/O (bank B)
Pin 94	I/O — User I/O (bank B)
Pin 95	I/O — User I/O (bank B)
Pin 96	I/O — User I/O (bank B)
Pin 97	I/O — User I/O (bank B)
Pin 98	I/O — User I/O (bank B)
Pin 99	I/O — User I/O (bank B)
Pin 100	I/O — User I/O (bank B)
Pin 101	I/O — User I/O (bank B)
Pin 102	I/O — User I/O (bank B)
Pin 103	I/O — User I/O (bank B)
Pin 104	I/O — User I/O (bank B)
Pin 105	I/O — User I/O (bank B)
Pin 106	I/O — User I/O (bank B)
Pin 107	VCCIO_B — I/O bank B supply (3.3V or 5.0V)
Pin 108	I/O — User I/O (bank B)
Pin 109	I/O — User I/O (bank B)
Pin 110	I/O — User I/O (bank B)
Pin 111	I/O — User I/O (bank B)
Pin 112	GND — Ground
Pin 113	I/O — User I/O (bank B)
Pin 114	I/O — User I/O (bank B)
Pin 115	I/O — User I/O (bank B)
Pin 116	I/O — User I/O (bank B)
Pin 117	I/O — User I/O (bank B)
Pin 118	I/O — User I/O (bank B)
Pin 119	I/O — User I/O (bank B)
Pin 120	I/O — User I/O (bank B)
Pin 121	I/O — User I/O (bank B)
Pin 122	I/O — User I/O (bank B)
Pin 123	I/O — User I/O (bank B)
Pin 124	I/O — User I/O (bank B)
Pin 125	I/O — User I/O (bank B)
Pin 126	I/O — User I/O (bank B)
Pin 127	I/O — User I/O (bank B)
Pin 128	I/O — User I/O (bank B)
Pin 129	I/O — User I/O (bank B)
Pin 130	I/O — User I/O (bank B)
Pin 131	I/O — User I/O (bank B)
Pin 132	I/O — User I/O (bank B)
Pin 133	I/O — User I/O (bank B)
Pin 134	I/O — User I/O (bank B)
Pin 135	I/O — User I/O (bank B)
Pin 136	I/O — User I/O (bank B)
Pin 137	I/O — User I/O (bank B)
Pin 138	I/O — User I/O (bank B)
Pin 139	I/O — User I/O (bank B)
Pin 140	I/O — User I/O (bank B)
Pin 141	I/O — User I/O (bank B)
Pin 142	I/O — User I/O (bank B)
Pin 143	I/O — User I/O (bank B)
Pin 144	I/O — User I/O (bank B)

Safe Operating Area (SOA) & Thermal Characteristics

No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.

Typical Applications

EPF8820ATC144-1 is suitable for 7 applications: Glue Logic Replacement, Custom State-Machine Controllers, Bus-Interface Bridging, Peripheral Emulation, Embedded Computing Subsystems, Legacy Telecom Datapath, Test & Measurement Front-End.

🔧

Glue Logic Replacement

The EPF8820ATC144-1's 672 logic cells, 84 LABs, and 112 user I/Os are well-matched to consolidating scattered discrete TTL/CMOS glue logic on legacy boards. With up to 1,500 flip-flops available, the part can replace dozens of 74-series packages while preserving the 5V supply and parallel-EPROM configuration flow familiar to FLEX 8000 designs. Unlike an ASIC, the device is in-circuit reconfigurable (ICR), allowing post-layout bug fixes without board rework.

Recommended

EPC1 (Serial configuration device) EPC1064 (Serial configuration memory)

🏭

Custom State-Machine Controllers

The FLEX 8000 register-rich architecture gives the EPF8820ATC144-1 the flip-flop density required for complex finite state machines used in industrial control, telecom, and instrumentation. Designers can encode wide state vectors, large microsequencers, and bit-serial protocols across the 1,500 available flip-flops. The 144-pin TQFP exposes enough I/O for parallel sensor buses and discrete control lines while keeping the board on a 5V rail.

Recommended

EPC1213 (Serial configuration device) EPC1441 (Serial configuration memory)

🌐

Bus-Interface Bridging

Bridging between legacy 5V buses (ISA, PC/104, VME, parallel peripheral) and downstream 3.3V devices is straightforward with the EPF8820ATC144-1 thanks to its MultiVolt I/O feature. Each I/O bank can be set independently for 3.3V or 5.0V operation, allowing level translation and protocol conversion in a single chip. The 112 user I/Os provide generous headroom for parallel address/data/control bridging without external buffers.

Recommended

EPC1 (Configuration device for production programming)

🖥️

Peripheral Emulation

The EPF8820ATC144-1 is widely used to emulate obsolete peripheral controllers, custom ASICs, and legacy video or DMA engines in long-lifecycle industrial systems. Its SRAM-based configuration allows the emulation bitstream to be updated as the host system evolves, while the JTAG (IEEE 1149.1) interface simplifies bench bring-up and field diagnostics. Designers can replace a discontinued IC with the same board footprint while preserving original software behavior.

Recommended

EPC1064 (Configuration memory for emulation bitstreams)

⚡

Embedded Computing Subsystems

In embedded designs, the EPF8820ATC144-1 serves as a coprocessor or peripheral controller alongside a microprocessor or microcontroller. Its 672 logic cells support small RISC cores, DMA engines, and custom interrupt controllers, while 112 I/Os expose the address/data buses needed for tight CPU coupling. The 5V supply and 144-pin TQFP keep it compatible with legacy MCU/DSP baseboards.

Recommended

EPC1441 (High-density serial configuration memory)

🌐

Legacy Telecom Datapath

Datapath and framing functions in legacy telecom line cards and base-station controllers fit naturally into the EPF8820ATC144-1's register-rich architecture. Bit-serial protocols, framing/deframing, HDLC controllers, and small CRC engines map efficiently to the FLEX 8000 LAB structure, and the 112 I/Os handle parallel PCM/TDM buses. Designers can hold 5V system power while gaining a programmable replacement for obsolete ASICs.

Recommended

EPC1 (Serial configuration device for telecom-grade programming)

🔧

Test & Measurement Front-End

The EPF8820ATC144-1's MultiVolt I/O and 112 user I/Os suit it to custom test and measurement front-ends where mixed-voltage analog-to-digital converters and parallel display buses must be sequenced and timed. The 1,500-flip-flop headroom supports custom trigger logic, counters, and timing generators that would otherwise require multiple discrete PLDs. JTAG access speeds bench bring-up and in-field firmware updates.

Recommended

EPC1213 (Configuration device for production)

Recommended Products Summary

EPC1 Serial configuration device Used in: Glue Logic Replacement, Bus-Interface Bridging, Legacy Telecom Datapath EPC1064 Serial configuration memory Used in: Glue Logic Replacement, Peripheral Emulation EPC1213 Serial configuration device Used in: Custom State-Machine Controllers, Test & Measurement Front-End EPC1441 Serial configuration memory Used in: Custom State-Machine Controllers, Embedded Computing Subsystems

What is the EPF8820ATC144-1?

The EPF8820ATC144-1 is a member of Altera's FLEX 8000 family of CMOS SRAM-based FPGAs. It contains 672 logic cells organized into 84 Logic Array Blocks, provides 112 user I/Os, and is housed in a 144-pin TQFP package. It operates from a 5V supply and supports MultiVolt I/O for 3.3V or 5.0V signaling. The trailing "-1" denotes the slowest speed grade.

How many logic cells and LABs does the EPF8820ATC144-1 have?

The EPF8820ATC144-1 contains 672 logic cells distributed across 84 Logic Array Blocks (LABs). It also provides up to 1,500 flip-flops and approximately 8,000 usable gates, making it a register-rich device for its era. These resources support pipelined datapaths and small glue-logic subsystems.

What is the difference between EPF8820ATC144-1, -2, -3, and -4?

The trailing suffix indicates the speed grade: -1 is the slowest, -4 is the fastest. Pinout and logic resources are identical across speed grades; only timing closure differs. Choose -1 for cost-sensitive, non-timing-critical applications and -4 where higher Fmax is required.

What configuration memory does the EPF8820ATC144-1 use?

The EPF8820ATC144-1 is SRAM-based and loses its configuration when power is removed. It must be loaded at power-up from an Altera serial configuration device such as EPC1, EPC1064, EPC1213, or EPC1441, or from an industry-standard parallel EPROM driven by a system controller. The MultiVolt I/O interface supports 3.3V or 5.0V configuration peripherals.

Where can I buy the EPF8820ATC144-1?

The EPF8820ATC144-1 is an obsolete Altera/Intel part and is not actively stocked at major franchised distributors. Used and refurbished inventory can occasionally be sourced through specialist brokers, legacy-component distributors, and auction platforms. Confirm authenticity, lot date code, and lead-free status before purchase.

What is the price of the EPF8820ATC144-1 in 2026?

Because the EPF8820ATC144-1 is obsolete, list pricing is not maintained by franchised distributors. As of 2026-09-12, secondary-market prices range widely based on lot size, condition, and traceability. The XAIPART quote tiers above (1 / 10 / 100 / 500 / 1000 pcs) reflect indicative broker pricing as of that date and are subject to availability.

What is the lead time for the EPF8820ATC144-1?

Lead time for the obsolete EPF8820ATC144-1 is variable because it depends on broker stock. Franchised-distributor lead times are not applicable. Plan for 4-12 weeks when sourcing through authorized brokers and validate the date code and traceability paperwork with the supplier before placing a production order.

Is the EPF8820ATC144-1 still in production?

No. The EPF8820ATC144-1 belongs to the FLEX 8000 family, which was discontinued by Altera (now Intel) and is classified as obsolete. For new designs, Intel recommends migrating to the Cyclone IV or Cyclone V families, which provide higher logic density, lower power, and active lifecycle support.

What is the difference between EPF8820ATC144-1 and EPF8820ATC144-4?

Both parts share the same 144-pin TQFP package, 672 logic cells, 84 LABs, 112 user I/Os, and 5V supply. They differ only in speed grade: -1 is the slowest and -4 is the fastest. Logic, pinout, and footprint are identical, so they are drop-in compatible when timing margins allow.

Can the EPF8820ATC144-1 be replaced by a Cyclone device?

Direct drop-in replacement on the same 144-pin TQFP footprint is not possible because Cyclone IV and Cyclone V devices use different packages, I/O standards, configuration schemes, and Quartus device libraries. A PCB redesign is required, but the migration typically reduces power, increases performance, and improves tool support.

Where can I download the EPF8820ATC144-1 datasheet PDF?

The Altera/Intel datasheet for the FLEX 8000 family, which covers the EPF8820ATC144-1, is available through legacy Altera documentation mirrors such as alterasemi.com and alldatasheet.com. Search the family datasheet (FLEX 8000 Device Family datasheet) rather than a per-pin PDF because FLEX 8000 documentation is consolidated at the family level.

What package does the EPF8820ATC144-1 use?

The EPF8820ATC144-1 uses a 144-pin Thin Quad Flat Pack (TQFP) package, 22 mm x 22 mm body with 0.5 mm pitch and gull-wing leads. Pin 1 is located by the standard TQFP indicator (dot or beveled edge) and the pinout is documented in the FLEX 8000 family datasheet.

What is the pinout of the EPF8820ATC144-1?

The full 144-pin TQFP pinout is documented in the FLEX 8000 family datasheet. The package exposes dedicated JTAG pins (TCK, TMS, TDI, TDO), configuration pins (nCONFIG, nSTATUS, CONF_DONE, MSEL[0..2], DCLK, DATA[0..7] in parallel mode), global clock pins, and 112 user I/O pins assigned to I/O banks A through D.

Is the EPF8820ATC144-1 RoHS compliant?

RoHS compliance for the EPF8820ATC144-1 cannot be confirmed from current Altera/Intel documentation because the part is obsolete. Many legacy FLEX 8000 devices were originally Pb-bearing and later re-released as lead-free variants; confirm the specific finish (Sn/Pb vs lead-free) with the date code and manufacturer paperwork before use in a RoHS-restricted build.

Hey Google, can the EPF8820ATC144-1 be swapped with EPF8282ATC100-3?

No. The EPF8820ATC144-1 has 672 logic cells in a 144-pin TQFP, while the EPF8282ATC100-3 has only 208 logic cells in a 100-pin TQFP. Pin counts, package dimensions, and logic capacity differ significantly, so they are not drop-in compatible. The EPF8282 may serve as a low-density functional alternative but requires PCB redesign.

Engineering reference data for EPF8820ATC144-1 — comparison, design guidance, and compliance information.

Selection Guide

Choose the EPF8820ATC144-1 when you need a cost-optimized, 5V-tolerant FPGA with 672 logic cells in a 144-pin TQFP and timing margins are generous enough to accept the slowest FLEX 8000 speed grade. It is well-suited to glue-logic replacement, custom state-machine controllers, bus-bridging, and legacy peripheral emulation in industrial and telecom systems where 5V rails are still in use. For timing-critical paths, upgrade to the -2, -3, or -4 speed grade of the same die - all share the identical 144-pin TQFP footprint. For RoHS-restricted builds, migrate to the "N" suffix variant (EPF8820ATC144-2N, -3N, or -4N) which adds a lead-free finish. For new designs, prefer an active Cyclone IV or Cyclone V device - the FLEX 8000 family is obsolete and supported only through broker channels.

Comparison with Alternatives

Parameter	This Product	EPF8820ATC144-4	EPF8820ATC144-3	EPF8820ATC144-2	EPF8820ATC144-4N
Brand	Altera	Altera	Altera	Altera	Altera
Package	144-pin TQFP	144-pin TQFP - same	144-pin TQFP - same	144-pin TQFP - same	144-pin TQFP - same
Logic Cells	672	672	672	672	672
LABs	84	84	84	84	84
User I/Os	112	112	112	112	112
Speed Grade	-1 (slowest)	-4 (fastest)	-3	-2	-4N (fastest, lead-free)
Supply Voltage	5V (MultiVolt I/O)	5V (MultiVolt I/O)	5V (MultiVolt I/O)	5V (MultiVolt I/O)	5V (MultiVolt I/O)
Operating Temperature	0C to 70C (commercial)	0C to 70C (commercial)	0C to 70C (commercial)	0C to 70C (commercial)	0C to 70C (commercial)
Lifecycle Status	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete
Lead-Free Finish ("N" suffix)	No (Pb-bearing)	No	No	No	Yes

Key Differentiators

Identical footprint, different speed grade (vs EPF8820ATC144-4)
5V MultiVolt I/O architecture (vs EPF8820ATC144-3N (also Altera FLEX 8000))
Lead-free variant available in same footprint (vs EPF8820ATC144-4N)

Design Notes

The EPF8820ATC144-1 requires a stable 5.0V VCCINT (core) supply and per-bank VCCIO supplies that can be set independently for 3.3V or 5.0V operation. Place 0.1uF decoupling capacitors as close as possible to every VCCINT and VCCIO pin, and add bulk 10uF-47uF tantalum or ceramic capacitors near each supply pin. Power-up sequencing must satisfy the FLEX 8000 requirements: VCCINT and VCCIO must ramp monotonically to ensure proper configuration.

FLEX 8000 devices are SRAM-based and lose their configuration when power is removed. A non-volatile configuration source (EPC1, EPC1064, EPC1213, EPC1441, or parallel EPROM) is required for production boards. The nCONFIG, nSTATUS, and CONF_DONE pins must be pulled and monitored per the datasheet; failing to do so results in configuration failure at power-up. During JTAG programming, ensure the JTAG chain order matches the BSDL file before asserting nCONFIG.

Route configuration and JTAG signals (TCK, TMS, TDI, TDO, nCONFIG, nSTATUS, CONF_DONE, MSEL, DCLK, DATA[0..7]) away from fast-switching user I/O to avoid coupling into the configuration logic. Keep global clock pins short and guarded by ground on both sides. Because the 144-pin TQFP has 0.5 mm pitch, use 0.15 mm/0.20 mm trace-and-space rules and verify the PCB vendor supports fine-line manufacturing.

MultiVolt I/O allows each bank to operate at 3.3V or 5.0V but level translation is only between VCCIO and the FPGA core - never between banks with different VCCIO unless a level-shifting buffer is added. When mixing 3.3V and 5.0V peripherals, place 5V-tolerant buffers on 3.3V outputs that drive 5V inputs to prevent leakage. Use IBIS simulation to validate edge rates on parallel buses that exceed 50 MHz.

Compliance Information

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

Lead Free

Halogen Free

Unknown

Conflict Minerals

Unknown

The EPF8820ATC144-1 (without "N" suffix) is the original Pb-bearing finish; "N" suffix variants (e.g. EPF8820ATC144-4N) are lead-free and RoHS-compliant. Confirm the exact finish by the date code and supplier paperwork before use in RoHS-restricted builds.

Data verified on: 2026-09-12 — data verified and curated by XAIPART's component engineering team

Sources: Distributor, Distributor, Manufacturer_Datasheet, Manufacturer_Datasheet, Manufacturer_Datasheet, Manufacturer_Product_Page, Distributor, Distributor, Octopart, Octopart

Related Components & Terms

Altera Intel EPF8820ATC144-1 EPF8820ATC144-4 EPF8820ATC144-3 EPF8820ATC144-2 EPF8820ATC144-4N EPF8820ATC144-3N EPF8820ATC144-2N FLEX 8000 FPGA Field Programmable Gate Array programmable logic device PLD Logic Array Block LAB logic cell flip-flop SRAM configuration MultiVolt I/O JTAG IEEE 1149.1 TQFP 144-pin TQFP gull-wing lead 5V CMOS EPC1 EPC1064 EPC1213 EPC1441 parallel EPROM configuration device RoHS Cyclone IV Cyclone V boundary-scan test BSDL lead-free finish obsolete semiconductor glue logic state machine bus interface bridging peripheral emulation