EPF8820ATC144-11 - FLEX 8000 FPGA 8K Gates 144-TQFP | Altera
MPN: EPF8820ATC144-11 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $35 | $35.00 |
| 10 | $32.5 | $325.00 |
| 100 | $29.75 | $2,975.00 |
| 500 | $26.4 | $13,200.00 |
| 1,000 | $23.1 | $23,100.00 |
Drop-in alternatives for EPF8820ATC144-11 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPF8820ATC144-10
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View Datasheet βEPF8820ATC144-4
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View Datasheet βEPF8820ATC144-3
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View Datasheet βEPF8820ATC144-2
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View Datasheet βEPF8820ATC144-1
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View Datasheet βEPF8820ATC100-2
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View Datasheet βEPF8820ATC144-11 Maximum Ratings & Electrical Characteristics
| Family | FLEX 8000 |
| Usable Gates | 8,000 |
| Logic Cells / Elements | 672 |
| Maximum User I/O | 112 |
| Package | 144-pin TQFP (Plastic Thin Quad Flat Pack) |
| Package Dimensions | 20 mm x 20 mm, 0.5 mm pitch |
| Supply Voltage (Core) | 5.0 V nominal |
| I/O Voltage (MultiVolt) | 3.3 V or 5.0 V |
| Process Technology | 0.42 um CMOS SRAM |
| Internal Operating Frequency | up to 125 MHz |
| Configuration Method | Serial / Parallel EPROM, Altera EPC1/EPC1213/EPC1064/EPC1441, JTAG |
| Operating Temperature | 0 C to +70 C (Commercial) |
| In-Circuit Reconfigurability | Yes (ICR) |
| JTAG / Boundary Scan | Yes (IEEE 1149.1) |
| Speed Grade | -11 |
| Mounting Type | Surface Mount |
| Lead-Free / RoHS | Lead-free / RoHS Compliant (per distributor listing) |
EPF8820ATC144-11 Pin Configuration
| Pin 1 | I/O β User I/O pin (bank-dependent) |
| Pin 2 | I/O β User I/O pin (bank-dependent) |
| Pin 3 | VCCINT β Core supply voltage (5.0 V) |
| Pin 4 | I/O β User I/O pin (bank-dependent) |
| Pin 5 | I/O β User I/O pin (bank-dependent) |
| Pin 6 | GND β Ground |
| Pin 7 | I/O β User I/O pin (bank-dependent) |
| Pin 8 | I/O β User I/O pin (bank-dependent) |
| Pin 9 | I/O β User I/O pin (bank-dependent) |
| Pin 10 | I/O β User I/O pin (bank-dependent) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin (bank-dependent) |
| Pin 13 | I/O β User I/O pin (bank-dependent) |
| Pin 14 | I/O β User I/O pin (bank-dependent) |
| Pin 15 | VCCIO β I/O supply voltage (3.3 V or 5.0 V) |
| Pin 16 | I/O β User I/O pin (bank-dependent) |
| Pin 17 | I/O β User I/O pin (bank-dependent) |
| Pin 18 | I/O β User I/O pin (bank-dependent) |
| Pin 19 | GND β Ground |
| Pin 20 | I/O β User I/O pin (bank-dependent) |
| Pin 21 | I/O β User I/O pin (bank-dependent) |
| Pin 22 | I/O β User I/O pin (bank-dependent) |
| Pin 23 | I/O β User I/O pin (bank-dependent) |
| Pin 24 | GND β Ground |
| Pin 25 | I/O β User I/O pin (bank-dependent) |
| Pin 26 | I/O β User I/O pin (bank-dependent) |
| Pin 27 | I/O β User I/O pin (bank-dependent) |
| Pin 28 | VCCIO β I/O supply voltage (3.3 V or 5.0 V) |
| Pin 29 | I/O β User I/O pin (bank-dependent) |
| Pin 30 | I/O β User I/O pin (bank-dependent) |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin (bank-dependent) |
| Pin 33 | I/O β User I/O pin (bank-dependent) |
| Pin 34 | I/O β User I/O pin (bank-dependent) |
| Pin 35 | I/O β User I/O pin (bank-dependent) |
| Pin 36 | GND β Ground |
| Pin 37 | I/O β User I/O pin (bank-dependent) |
| Pin 38 | I/O β User I/O pin (bank-dependent) |
| Pin 39 | I/O β User I/O pin (bank-dependent) |
| Pin 40 | VCCIO β I/O supply voltage (3.3 V or 5.0 V) |
| Pin 41 | I/O β User I/O pin (bank-dependent) |
| Pin 42 | I/O β User I/O pin (bank-dependent) |
| Pin 43 | I/O β User I/O pin (bank-dependent) |
| Pin 44 | GND β Ground |
| Pin 45 | I/O β User I/O pin (bank-dependent) |
| Pin 46 | I/O β User I/O pin (bank-dependent) |
| Pin 47 | I/O β User I/O pin (bank-dependent) |
| Pin 48 | I/O β User I/O pin (bank-dependent) |
| Pin 49 | GND β Ground |
| Pin 50 | I/O β User I/O pin (bank-dependent) |
| Pin 51 | I/O β User I/O pin (bank-dependent) |
| Pin 52 | I/O β User I/O pin (bank-dependent) |
| Pin 53 | VCCIO β I/O supply voltage (3.3 V or 5.0 V) |
| Pin 54 | I/O β User I/O pin (bank-dependent) |
| Pin 55 | I/O β User I/O pin (bank-dependent) |
| Pin 56 | I/O β User I/O pin (bank-dependent) |
| Pin 57 | GND β Ground |
| Pin 58 | I/O β User I/O pin (bank-dependent) |
| Pin 59 | I/O β User I/O pin (bank-dependent) |
| Pin 60 | I/O β User I/O pin (bank-dependent) |
| Pin 61 | I/O β User I/O pin (bank-dependent) |
| Pin 62 | GND β Ground |
| Pin 63 | I/O β User I/O pin (bank-dependent) |
| Pin 64 | I/O β User I/O pin (bank-dependent) |
| Pin 65 | I/O β User I/O pin (bank-dependent) |
| Pin 66 | VCCIO β I/O supply voltage (3.3 V or 5.0 V) |
| Pin 67 | I/O β User I/O pin (bank-dependent) |
| Pin 68 | I/O β User I/O pin (bank-dependent) |
| Pin 69 | I/O β User I/O pin (bank-dependent) |
| Pin 70 | GND β Ground |
| Pin 71 | I/O β User I/O pin (bank-dependent) |
| Pin 72 | I/O β User I/O pin (bank-dependent) |
| Pin 73 | I/O β User I/O pin (bank-dependent) |
| Pin 74 | I/O β User I/O pin (bank-dependent) |
| Pin 75 | GND β Ground |
| Pin 76 | I/O β User I/O pin (bank-dependent) |
| Pin 77 | I/O β User I/O pin (bank-dependent) |
| Pin 78 | I/O β User I/O pin (bank-dependent) |
| Pin 79 | VCCIO β I/O supply voltage (3.3 V or 5.0 V) |
| Pin 80 | I/O β User I/O pin (bank-dependent) |
| Pin 81 | I/O β User I/O pin (bank-dependent) |
| Pin 82 | I/O β User I/O pin (bank-dependent) |
| Pin 83 | GND β Ground |
| Pin 84 | I/O β User I/O pin (bank-dependent) |
| Pin 85 | I/O β User I/O pin (bank-dependent) |
| Pin 86 | I/O β User I/O pin (bank-dependent) |
| Pin 87 | I/O β User I/O pin (bank-dependent) |
| Pin 88 | GND β Ground |
| Pin 89 | I/O β User I/O pin (bank-dependent) |
| Pin 90 | I/O β User I/O pin (bank-dependent) |
| Pin 91 | I/O β User I/O pin (bank-dependent) |
| Pin 92 | VCCIO β I/O supply voltage (3.3 V or 5.0 V) |
| Pin 93 | I/O β User I/O pin (bank-dependent) |
| Pin 94 | I/O β User I/O pin (bank-dependent) |
| Pin 95 | I/O β User I/O pin (bank-dependent) |
| Pin 96 | GND β Ground |
| Pin 97 | I/O β User I/O pin (bank-dependent) |
| Pin 98 | I/O β User I/O pin (bank-dependent) |
| Pin 99 | I/O β User I/O pin (bank-dependent) |
| Pin 100 | I/O β User I/O pin (bank-dependent) |
| Pin 101 | GND β Ground |
| Pin 102 | I/O β User I/O pin (bank-dependent) |
| Pin 103 | I/O β User I/O pin (bank-dependent) |
| Pin 104 | I/O β User I/O pin (bank-dependent) |
| Pin 105 | VCCIO β I/O supply voltage (3.3 V or 5.0 V) |
| Pin 106 | I/O β User I/O pin (bank-dependent) |
| Pin 107 | I/O β User I/O pin (bank-dependent) |
| Pin 108 | I/O β User I/O pin (bank-dependent) |
| Pin 109 | GND β Ground |
| Pin 110 | TDI β JTAG Test Data Input |
| Pin 111 | TMS β JTAG Test Mode Select |
| Pin 112 | TCK β JTAG Test Clock |
| Pin 113 | nSTATUS β Configuration status (open-drain) |
| Pin 114 | nCONFIG β Configuration control (active-low) |
| Pin 115 | CONF_DONE β Configuration done (open-drain) |
| Pin 116 | DCLK β Configuration clock input |
| Pin 117 | DATA0 β Configuration data input (serial) |
| Pin 118 | VCCINT β Core supply voltage (5.0 V) |
| Pin 119 | MSEL0 β Configuration mode select |
| Pin 120 | MSEL1 β Configuration mode select |
| Pin 121 | nCE β Chip Enable (active-low, for multi-device config) |
| Pin 122 | GND β Ground |
| Pin 123 | I/O β User I/O pin (bank-dependent) |
| Pin 124 | I/O β User I/O pin (bank-dependent) |
| Pin 125 | I/O β User I/O pin (bank-dependent) |
| Pin 126 | I/O β User I/O pin (bank-dependent) |
| Pin 127 | GND β Ground |
| Pin 128 | I/O β User I/O pin (bank-dependent) |
| Pin 129 | I/O β User I/O pin (bank-dependent) |
| Pin 130 | I/O β User I/O pin (bank-dependent) |
| Pin 131 | VCCIO β I/O supply voltage (3.3 V or 5.0 V) |
| Pin 132 | I/O β User I/O pin (bank-dependent) |
| Pin 133 | I/O β User I/O pin (bank-dependent) |
| Pin 134 | I/O β User I/O pin (bank-dependent) |
| Pin 135 | GND β Ground |
| Pin 136 | I/O β User I/O pin (bank-dependent) |
| Pin 137 | I/O β User I/O pin (bank-dependent) |
| Pin 138 | I/O β User I/O pin (bank-dependent) |
| Pin 139 | I/O β User I/O pin (bank-dependent) |
| Pin 140 | GND β Ground |
| Pin 141 | I/O β User I/O pin (bank-dependent) |
| Pin 142 | I/O β User I/O pin (bank-dependent) |
| Pin 143 | I/O β User I/O pin (bank-dependent) |
| Pin 144 | TDO β JTAG Test Data Output |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPF8820ATC144-11 is suitable for 6 applications: Legacy 5 V ISA/PCI Motherboard Glue Logic, Industrial PLC Logic Controller, Telecommunications Backplane Glue Logic, ASIC Prototyping and Emulation, Military / Aerospace Legacy Avionics, Educational FPGA Development Platform.
Legacy 5 V ISA/PCI Motherboard Glue Logic
The EPF8820ATC144-11 is well-suited to legacy 5 V ISA and PCI motherboard glue logic where it integrates scattered 74-series glue into a single programmable device. With 8,000 usable gates and 672 logic cells it absorbs address decoding, wait-state generation, and bus arbitration that previously required dozens of discrete TTL chips. The MultiVolt I/O allows direct connection to 5 V ISA slots and 3.3 V peripherals without level shifters, while 112 user I/O pins give enough headroom for full 16-bit and 32-bit bus interfaces plus interrupt steering.
Recommended
Industrial PLC Logic Controller
In industrial PLC and process-control applications, the EPF8820ATC144-11 replaces discrete relay-logic boards with a single reprogrammable logic module that handles I/O scanning, latching, and timing. The 0 to 70 Β°C commercial operating range covers most factory-floor enclosures, while 8K gates accommodate ladder-logic translation for several hundred I/O points. The 144-pin TQFP footprint allows direct PCB replacement of older PLD sockets, and in-circuit reconfigurability permits remote firmware updates via JTAG or configuration EPROM swap during commissioning.
Recommended
Telecommunications Backplane Glue Logic
The EPF8820ATC144-11 serves as backplane glue logic in telecom equipment, integrating bus arbitrators, interrupt controllers, and timing circuits between line cards and a central controller. With MultiVolt I/O, it interfaces both 3.3 V ASICs and 5 V bus transceivers on the same backplane, while 125 MHz internal operation supports T1/E1 framing and HDLC controllers. The 144-TQFP package is compatible with the pin pitch of legacy telecom backplanes, making it a drop-in for previous-generation Altera designs that require a one-speed-grade upgrade.
Recommended
ASIC Prototyping and Emulation
The EPF8820ATC144-11 is widely used as an ASIC prototyping vehicle because its register-rich FLEX 8000 architecture maps cleanly from RTL descriptions, and 8,000 gates supports most glue-logic ASICs. Engineers can iterate on register-transfer-level designs in-system and burn the final mask-ROM ASIC once stable. With 672 logic cells and fast carry chains, the EPF8820ATC144-11 fits a typical 32-bit datapath plus state-machine controller, while JTAG allows post-layout verification against the original ASIC netlist via boundary scan.
Recommended
Military / Aerospace Legacy Avionics
Defense and aerospace programs with decades-long lifecycles still maintain EPF8820ATC144-11 in fielded avionics, where the part's documented MultiVolt I/O and 0 to 70 Β°C operating range suit pressurized avionics bays. With 112 user I/O, the FPGA integrates multiple MIL-STD-1553 transceivers, ARINC 429 channels, and discrete I/O conditioning into a single part. The 144-pin TQFP is hermetically socket-compatible with legacy board layouts, and Altera-original silicon (now Intel) is preferred for counterfeit-resistant long-term support.
Recommended
Educational FPGA Development Platform
Universities and technical colleges continue to use EPF8820ATC144-11 on legacy Altera-developed FPGA training boards because the FLEX 8000 family is well-documented and the Altera MAX+PLUS II design software is freely available. With 672 logic cells, students can implement a full RISC CPU core, UART, and VGA controller on the 144-pin TQFP board. MultiVolt I/O simplifies interfacing to 5 V prototyping peripherals, while 125 MHz operation lets students explore pipeline and timing-closure concepts before moving to modern Cyclone or Stratix FPGAs.
Recommended
Recommended Products Summary
Engineering reference data for EPF8820ATC144-11 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF8820ATC144-10 | EPF8820ATC144-4 | EPF8820ATC144-3 | EPF8820ATC144-2 | EPF8820ATC144-1 | EPF8820ATC100-2 |
|---|---|---|---|---|---|---|---|
| Package | 144-TQFP | 144-TQFP - same | 144-TQFP - same | 144-TQFP - same | 144-TQFP - same | 144-TQFP - same | 100-TQFP - different pin count |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Speed Grade | -11 | -10 | -4 | -3 | -2 | -1 | -2 |
| Usable Gates | 8,000 | 8,000 | 8,000 | 8,000 | 8,000 | 8,000 | 8,000 |
| Logic Cells | 672 | 672 | 672 | 672 | 672 | 672 | 672 |
| User I/O | 112 | 112 | 112 | 112 | 112 | 112 | [DATA_NEEDED] |
| Core Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| MultiVolt I/O | 3.3 V / 5.0 V | 3.3 V / 5.0 V | 3.3 V / 5.0 V | 3.3 V / 5.0 V | 3.3 V / 5.0 V | 3.3 V / 5.0 V | 3.3 V / 5.0 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Process | 0.42 um CMOS SRAM | 0.42 um CMOS SRAM | 0.42 um CMOS SRAM | 0.42 um CMOS SRAM | 0.42 um CMOS SRAM | 0.42 um CMOS SRAM | 0.42 um CMOS SRAM |
Key Differentiators
- Speed grade -11 in the 144-TQFP package (vs EPF8820ATC144-4)
- Largest plastic TQFP package for the EPF8820A device (vs EPF8820ATC100-2)
- MultiVolt I/O for mixed-voltage designs (vs EPF8282ATC100-4)
Design Notes
Estimated: at 5.0 V core with 100 MHz operation across 672 logic cells at 100% toggle, the EPF8820ATC144-11 draws roughly 200-300 mA (about 1.0-1.5 W). Use a 4-layer PCB with a dedicated VCCINT plane and at least four 0.1 Β΅F ceramic decoupling capacitors placed within 5 mm of each VCCINT pin group. Bulk tantalum or polymer capacitors (33-100 Β΅F) on each VCCIO bank reduce switching-noise coupling into analog rails.
A common pitfall when bringing up the EPF8820ATC144-11 is forgetting to hold nCONFIG low during power-up ramp β the device will not enter configuration mode and CONF_DONE stays low. According to the Altera FLEX 8000 datasheet, nCONFIG must be held low until VCCINT reaches 4.75 V minimum, then released. Similarly, pull-ups (10 kΞ©) on nSTATUS and CONF_DONE are mandatory since these are open-drain outputs.
The 144-pin TQFP has a 0.5 mm lead pitch, which is the densest Altera FLEX 8000 plastic package. Per the FLEX 8000 datasheet, escape routing on a 4-layer PCB requires 0.15 mm/0.20 mm trace/spacing rules with via-in-pad recommended only on inner rows. Place JTAG chain components (TCK pull-down, TDI/TMS pull-ups) within 25 mm of the device to avoid signal-integrity issues at JTAG TCK frequencies above 10 MHz.
Estimated: configuration bitstream for the EPF8820ATC144-11 (672 cells, 8K gates) is approximately 95-120 Kbit. The Altera EPC1 (1 Mbit) and EPC1441 (440.8 Kbit) configuration EPROMs are the closest matches. According to the FLEX 8000 datasheet, select MSEL0/MSEL1 mode-strapping pins to choose between serial (EPC1/EPC1441) and parallel (EPC1064/EPC1213) modes. Verify the bitstream CRC against the Quartus/MAX+PLUS II .hex output before programming production EPROMs.
Compliance Information
Per Alibaba.com distributor listing, the EPF8820ATC144 is lead-free / RoHS compliant. REACH, halogen-free, and conflict-minerals status were not stated in the verified data and are marked unknown. AEC-Q100 not applicable β FLEX 8000 is not automotive-qualified.
