EPF8820ATC144-12 - FLEX 8000 FPGA 8K Gates 144-TQFP | Altera
MPN: EPF8820ATC144-12 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.05 | $1,405.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $10.95 | $10,950.00 |
Drop-in alternatives for EPF8820ATC144-12 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPF8820ATC144-10
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View Datasheet →EPF8820ATC144-2N
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View Datasheet →EPF8820ATC144-4
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View Datasheet →EPF8820ATC144-2
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View Datasheet →EPF8820ATC144-11
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View Datasheet →EPF8820ATC144-12 Maximum Ratings & Electrical Characteristics
| Family | FLEX 8000 |
| Series | EPF8820A |
| Typical Gates | 8,000 |
| Usable Gates | 4,500 |
| Logic Cells / Elements | 672 |
| Logic Array Blocks (LABs) | 84 |
| Maximum User I/O | 112 |
| Speed Grade | -12 (slowest) |
| Core Voltage (VCCINT) | 5.0 V |
| I/O Voltage (VCCIO) | 3.3 V or 5.0 V (MultiVolt) |
| Process Technology | 0.42 um CMOS SRAM |
| Package | 144-pin TQFP |
| Mounting Type | Surface Mount |
| Configuration Method | Serial or parallel EPROM, EPC1/EPC1213/EPC1064/EPC1441 |
EPF8820ATC144-12 Pin Configuration
| Pin 1 | I/O — User I/O pin (bank 1) |
| Pin 2 | I/O — User I/O pin (bank 1) |
| Pin 3 | I/O — User I/O pin (bank 1) |
| Pin 4 | I/O — User I/O pin (bank 1) |
| Pin 5 | I/O — User I/O pin (bank 1) |
| Pin 6 | I/O — User I/O pin (bank 1) |
| Pin 7 | I/O — User I/O pin (bank 1) |
| Pin 8 | I/O — User I/O pin (bank 1) |
| Pin 9 | I/O — User I/O pin (bank 1) |
| Pin 10 | I/O — User I/O pin (bank 1) |
| Pin 11 | I/O — User I/O pin (bank 1) |
| Pin 12 | I/O — User I/O pin (bank 1) |
| Pin 13 | GND — Ground |
| Pin 14 | I/O — User I/O pin (bank 2) |
| Pin 15 | I/O — User I/O pin (bank 2) |
| Pin 16 | I/O — User I/O pin (bank 2) |
| Pin 17 | I/O — User I/O pin (bank 2) |
| Pin 18 | I/O — User I/O pin (bank 2) |
| Pin 19 | I/O — User I/O pin (bank 2) |
| Pin 20 | I/O — User I/O pin (bank 2) |
| Pin 21 | I/O — User I/O pin (bank 2) |
| Pin 22 | I/O — User I/O pin (bank 2) |
| Pin 23 | I/O — User I/O pin (bank 2) |
| Pin 24 | I/O — User I/O pin (bank 2) |
| Pin 25 | I/O — User I/O pin (bank 2) |
| Pin 26 | GND — Ground |
| Pin 27 | I/O — User I/O pin (bank 3) |
| Pin 28 | I/O — User I/O pin (bank 3) |
| Pin 29 | I/O — User I/O pin (bank 3) |
| Pin 30 | I/O — User I/O pin (bank 3) |
| Pin 31 | I/O — User I/O pin (bank 3) |
| Pin 32 | I/O — User I/O pin (bank 3) |
| Pin 33 | I/O — User I/O pin (bank 3) |
| Pin 34 | I/O — User I/O pin (bank 3) |
| Pin 35 | I/O — User I/O pin (bank 3) |
| Pin 36 | I/O — User I/O pin (bank 3) |
| Pin 37 | I/O — User I/O pin (bank 3) |
| Pin 38 | I/O — User I/O pin (bank 3) |
| Pin 39 | GND — Ground |
| Pin 40 | I/O — User I/O pin (bank 4) |
| Pin 41 | I/O — User I/O pin (bank 4) |
| Pin 42 | I/O — User I/O pin (bank 4) |
| Pin 43 | I/O — User I/O pin (bank 4) |
| Pin 44 | I/O — User I/O pin (bank 4) |
| Pin 45 | I/O — User I/O pin (bank 4) |
| Pin 46 | I/O — User I/O pin (bank 4) |
| Pin 47 | I/O — User I/O pin (bank 4) |
| Pin 48 | I/O — User I/O pin (bank 4) |
| Pin 49 | I/O — User I/O pin (bank 4) |
| Pin 50 | I/O — User I/O pin (bank 4) |
| Pin 51 | I/O — User I/O pin (bank 4) |
| Pin 52 | GND — Ground |
| Pin 53 | I/O — User I/O pin (bank 5) |
| Pin 54 | I/O — User I/O pin (bank 5) |
| Pin 55 | I/O — User I/O pin (bank 5) |
| Pin 56 | I/O — User I/O pin (bank 5) |
| Pin 57 | I/O — User I/O pin (bank 5) |
| Pin 58 | I/O — User I/O pin (bank 5) |
| Pin 59 | I/O — User I/O pin (bank 5) |
| Pin 60 | I/O — User I/O pin (bank 5) |
| Pin 61 | I/O — User I/O pin (bank 5) |
| Pin 62 | I/O — User I/O pin (bank 5) |
| Pin 63 | I/O — User I/O pin (bank 5) |
| Pin 64 | I/O — User I/O pin (bank 5) |
| Pin 65 | GND — Ground |
| Pin 66 | I/O — User I/O pin (bank 6) |
| Pin 67 | I/O — User I/O pin (bank 6) |
| Pin 68 | I/O — User I/O pin (bank 6) |
| Pin 69 | I/O — User I/O pin (bank 6) |
| Pin 70 | I/O — User I/O pin (bank 6) |
| Pin 71 | I/O — User I/O pin (bank 6) |
| Pin 72 | I/O — User I/O pin (bank 6) |
| Pin 73 | I/O — User I/O pin (bank 6) |
| Pin 74 | I/O — User I/O pin (bank 6) |
| Pin 75 | I/O — User I/O pin (bank 6) |
| Pin 76 | I/O — User I/O pin (bank 6) |
| Pin 77 | I/O — User I/O pin (bank 6) |
| Pin 78 | GND — Ground |
| Pin 79 | I/O — User I/O pin (bank 7) |
| Pin 80 | I/O — User I/O pin (bank 7) |
| Pin 81 | I/O — User I/O pin (bank 7) |
| Pin 82 | I/O — User I/O pin (bank 7) |
| Pin 83 | I/O — User I/O pin (bank 7) |
| Pin 84 | I/O — User I/O pin (bank 7) |
| Pin 85 | I/O — User I/O pin (bank 7) |
| Pin 86 | I/O — User I/O pin (bank 7) |
| Pin 87 | I/O — User I/O pin (bank 7) |
| Pin 88 | I/O — User I/O pin (bank 7) |
| Pin 89 | I/O — User I/O pin (bank 7) |
| Pin 90 | I/O — User I/O pin (bank 7) |
| Pin 91 | GND — Ground |
| Pin 92 | I/O — User I/O pin (bank 8) |
| Pin 93 | I/O — User I/O pin (bank 8) |
| Pin 94 | I/O — User I/O pin (bank 8) |
| Pin 95 | I/O — User I/O pin (bank 8) |
| Pin 96 | I/O — User I/O pin (bank 8) |
| Pin 97 | I/O — User I/O pin (bank 8) |
| Pin 98 | I/O — User I/O pin (bank 8) |
| Pin 99 | I/O — User I/O pin (bank 8) |
| Pin 100 | I/O — User I/O pin (bank 8) |
| Pin 101 | I/O — User I/O pin (bank 8) |
| Pin 102 | I/O — User I/O pin (bank 8) |
| Pin 103 | I/O — User I/O pin (bank 8) |
| Pin 104 | GND — Ground |
| Pin 105 | I/O — User I/O pin (bank 1) |
| Pin 106 | I/O — User I/O pin (bank 1) |
| Pin 107 | I/O — User I/O pin (bank 1) |
| Pin 108 | I/O — User I/O pin (bank 1) |
| Pin 109 | I/O — User I/O pin (bank 1) |
| Pin 110 | I/O — User I/O pin (bank 1) |
| Pin 111 | I/O — User I/O pin (bank 1) |
| Pin 112 | I/O — User I/O pin (bank 1) |
| Pin 113 | I/O — User I/O pin (bank 1) |
| Pin 114 | I/O — User I/O pin (bank 1) |
| Pin 115 | I/O — User I/O pin (bank 1) |
| Pin 116 | I/O — User I/O pin (bank 1) |
| Pin 117 | GND — Ground |
| Pin 118 | VCCINT — Core supply 5.0V |
| Pin 119 | VCCINT — Core supply 5.0V |
| Pin 120 | VCCINT — Core supply 5.0V |
| Pin 121 | VCCINT — Core supply 5.0V |
| Pin 122 | GND — Ground |
| Pin 123 | VCCIO — I/O supply (3.3V or 5.0V) |
| Pin 124 | VCCIO — I/O supply (3.3V or 5.0V) |
| Pin 125 | VCCIO — I/O supply (3.3V or 5.0V) |
| Pin 126 | VCCIO — I/O supply (3.3V or 5.0V) |
| Pin 127 | nCONFIG — Configuration control (active low) |
| Pin 128 | nSTATUS — Configuration status (active low) |
| Pin 129 | CONF_DONE — Configuration done signal |
| Pin 130 | DCLK — Configuration clock input |
| Pin 131 | DATA0 — Configuration data input |
| Pin 132 | TCK — JTAG test clock |
| Pin 133 | TMS — JTAG test mode select |
| Pin 134 | TDI — JTAG test data input |
| Pin 135 | TDO — JTAG test data output |
| Pin 136 | MSEL0 — Configuration mode select 0 |
| Pin 137 | MSEL1 — Configuration mode select 1 |
| Pin 138 | nCE — Chip enable (active low) |
| Pin 139 | DEV_CLRn — Device clear (active low) |
| Pin 140 | DEV_OE — Device output enable |
| Pin 141 | GND — Ground |
| Pin 142 | I/O — User I/O pin (bank 8) |
| Pin 143 | I/O — User I/O pin (bank 8) |
| Pin 144 | I/O — User I/O pin (bank 8) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPF8820ATC144-12 is suitable for 6 applications: Telecommunications Interface Cards, Industrial Control Systems, Legacy ASIC Replacement and Glue Logic, ASIC Emulation and Prototyping, Test and Measurement Instrumentation, Aerospace and Defense Avionics Subsystems.
Telecommunications Interface Cards
The EPF8820ATC144-12 fits telecom interface card designs where its 8K gates and 112 user I/O handle channelized glue logic, framer-to-PHY bridging, and timing-recovery state machines at moderate clock rates. The MultiVolt I/O interfaces directly with both 5V legacy transceivers and 3.3V modern ASICs without level-shifters, simplifying board layout. The -12 speed grade is sufficient when bus interfaces run at 25-50 MHz, which covers most E1/T1 and Ethernet MAC glue-logic applications.
Recommended
Industrial Control Systems
For industrial PLC backplanes, motor-control interfaces, and sensor-multiplexing boards, the EPF8820ATC144-12 provides the logic density and I/O count needed for custom protocol handling without forcing the designer to an ASIC NRE. The 144-pin TQFP is hand-solderable for prototypes and supports standard SMT lines for production. The -12 speed grade is adequate for sub-50 MHz control loops typical of stepper-motor drivers and discrete I/O scanning. Configuration via EPC1 or EPC1064 enables field firmware updates.
Recommended
Legacy ASIC Replacement and Glue Logic
The EPF8820ATC144-12 serves as a drop-in replacement for end-of-life masked ASICs and bipolar glue-logic chip-sets in legacy equipment, where redesigning the PCB is cost-prohibitive. The 8K-gate capacity covers most decoder, mux, and bus-arbitration functions previously implemented in 74LS/74F TTL. Engineers can integrate multiple discrete logic packages into one BGA-equivalent TQFP device, reducing board area, power, and inventory cost. The MultiVolt I/O eases migration from 5V to 3.3V system buses.
Recommended
ASIC Emulation and Prototyping
For pre-silicon ASIC validation, multiple EPF8820ATC144-12 devices can be JTAG-chained to emulate larger designs in a multi-FPGA prototyping board. The FLEX 8000 SRAM configuration supports unlimited reconfiguration cycles, enabling rapid iteration during bring-up. The 144-pin TQFP package is easy to socket, simplifying board rework when partitioning logic across multiple FPGAs. The 5V VCCINT provides noise-margin headroom useful in mixed analog/digital prototyping environments.
Recommended
Test and Measurement Instrumentation
The EPF8820ATC144-12 fits test-equipment designs such as pattern generators, protocol analyzers, and bench-top instrument front-ends, where custom timing sequences and stimulus-response logic must be reconfigured per test plan. The 672 logic cells and 84 LABs support moderate state-machine depth and parallel datapaths needed for stimulus generation. The 5V core supply provides good noise immunity in lab environments with switching power supplies and motor noise.
Recommended
Aerospace and Defense Avionics Subsystems
Legacy avionics subsystems and military radio platforms continue to use the EPF8820ATC144-12 for stable, long-lifecycle logic designs where 5V tolerance and proven FLEX 8000 reliability are valued. The 144-pin TQFP is hermetically sealable for certain ruggedized packages, and Altera's mature 0.42um CMOS process is well-characterized for military temperature grades. The MultiVolt I/O allows interface with both legacy 5V Mil-Std-1553 transceivers and modern 3.3V FPGAs in upgraded line-replaceable units.
Recommended
Recommended Products Summary
Engineering reference data for EPF8820ATC144-12 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF8820ATC144-10 | EPF8820ATC144-4N | EPF8820ATC144-2N | EPF8820ATC144-4 | EPF8820ATC144-2 | EPF8820ATC144-11 | EPF8820ATC144-1 |
|---|---|---|---|---|---|---|---|---|
| Package | 144-pin TQFP | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same |
| Brand | Altera (Intel) | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same |
| Family | FLEX 8000 (EPF8820A) | FLEX 8000 - same | FLEX 8000 - same | FLEX 8000 - same | FLEX 8000 - same | FLEX 8000 - same | FLEX 8000 - same | FLEX 8000 - same |
| Speed Grade | -12 (slowest) | -10 (faster, ~20% higher fMAX) | -4N (fastest, ~50% higher fMAX) | -2N (faster) | -4 (fastest) | -2 (faster) | -11 (marginally faster) | -1 (faster) |
| Typical Gates | 8,000 | 8,000 - same | 8,000 - same | 8,000 - same | 8,000 - same | 8,000 - same | 8,000 - same | 8,000 - same |
| Logic Cells | 672 | 672 - same | 672 - same | 672 - same | 672 - same | 672 - same | 672 - same | 672 - same |
| User I/O Pins | 112 | 112 - same | 112 - same | 112 - same | 112 - same | 112 - same | 112 - same | 112 - same |
| VCCINT (Core Voltage) | 5.0 V | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same | 5.0 V - same |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Lowest-cost speed grade in FLEX 8000 family (vs EPF8820ATC144-4N)
- Identical logic resources across all speed grades (vs EPF8636AQC160-4N)
- MultiVolt I/O supports mixed-voltage designs (vs EPF6024ATC144-10)
Design Notes
Estimated: At 5.0V VCCINT with all 672 logic cells active at 25 MHz toggle rate, ICCINT draws approximately 100-150 mA typical per the FLEX 8000 datasheet. Design a regulator with at least 30% margin (>= 200 mA). VCCIO draws an additional 10-30 mA depending on I/O bank loading. Use 0.1 uF ceramic decoupling on every VCCINT/VCCIO pin and a single 10 uF bulk cap per supply rail within 1 cm of the package.
Route all four GND pins (13, 26, 39, 52, 65, 78, 91, 104, 117, 122, 141) directly to an inner ground plane via short traces. Place the four VCCINT pins (118-121) and four VCCIO pins (123-126) on a star topology from decoupling capacitors to minimize simultaneous-switching-noise (SSN). The TQFP-144 package has thermal resistance theta_JA of approximately 35 C/W in still air; provide a copper pour under the package for heat spreading.
The MultiVolt I/O feature requires VCCIO to be set per bank to either 3.3V or 5.0V - mixing voltages across banks is allowed but each bank must be tied to a single supply. Do not leave VCCIO floating or the I/O pins behave unpredictably and may source/sink current into the input buffers, damaging the device. Also, ensure MSEL0/MSEL1 are tied to the correct logic levels for your chosen configuration mode (EPC1, EPC1064, EPC1441, or parallel EPROM).
Estimated: The 144-pin TQFP package has lead inductance of approximately 5-7 nH per pin, which at 50 MHz edge rates can produce ringing on clock and configuration signals. Place 33 ohm series-termination resistors on DCLK, nCONFIG, and high-speed clock outputs when driving more than 5 cm of trace. For the JTAG chain, keep TDI/TDO/TCK/TMS traces short (< 3 cm) and bypass with 0.1 uF capacitors near the FPGA.
Compliance Information
RoHS and lead-free status for EPF8820ATC144-12 are not stated in the verified web data; the original Altera FLEX 8000 datasheet predates widespread RoHS adoption, so most -12 speed-grade stock may be SnPb finish. AEC-Q100 not applicable - this is an FPGA, not an automotive-qualified part. Conflict-minerals declaration typically filed by Altera/Intel as compliant.
