LTC2157CUP-14 - Dual 14-Bit 250Msps ADC | Analog Devices
MPN: LTC2157CUP-14 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $213.81 | $213.81 |
| 10 | $195.5 | $1,955.00 |
| 100 | $168.2 | $16,820.00 |
| 500 | $145.8 | $72,900.00 |
| 1,000 | $132.4 | $132,400.00 |
LTC2157CUP-14 Overview
An ADC (analog-to-digital converter) is a semiconductor device that converts continuous-time analog signals into discrete digital codes. The LTC2157-14 belongs to the pipelined ADC sub-family, which uses multiple cascaded low-resolution stages to achieve high sample rates while maintaining 14-bit resolution. Within the broader taxonomy, this part is a data converter -> ADC -> high-speed pipelined ADC -> dual-channel simultaneous-sampling ADC. Pipelined ADCs are widely used in communications infrastructure, defense electronics, and test and measurement equipment where both speed and resolution matter.
Key features of the LTC2157CUP-14 include a 1.5 Vp-p easy-to-drive input range, 1.25 GHz full-power sample-and-hold bandwidth, an optional clock duty cycle stabilizer, low-power sleep and nap modes, and a serial SPI port for per-channel configuration. The dual channels support either external or internal voltage reference and offer simultaneous sampling for I/Q or diversity receiver architectures. Pin-compatible 12-bit versions are available (LTC2157-12 family), allowing design scalability across resolution requirements.
The architecture is a 14-stage pipelined ADC with proprietary internal calibration, supporting 250 Msps per channel and offering 1:1 S/H-to-ADC ratio. The LVDS DDR outputs ease FPGA/ASIC capture and reduce pin count on the board. The internal reference simplifies BOM, while the external reference option enables system-wide gain calibration in high-linearity applications.
Typical applications include software-defined radio (SDR) receivers, MIMO LTE/WiMAX transceivers, multi-channel data acquisition systems, medical imaging front-ends, and radar/EW signal processing. The dual simultaneous-sampling channels also suit I/Q demodulation and direct-conversion receiver chains.
When designing with this part, place the analog input traces as a 50 ohm differential pair with controlled 100 ohm differential impedance, and keep LVDS outputs length-matched to within 50 mil to preserve timing margin. A solid ground plane beneath the QFN exposed pad is required for thermal dissipation at full sample rate.
This page synthesizes Analog Devices distributor pricing as of 2026-10-13, drop-in same-family alternatives from the LTC215x-14 series, and practical PCB/layout design notes not duplicated in the manufacturer datasheet.
Drop-in alternatives for LTC2157CUP-14 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2157CUP-14 (same form factor and footprint) — differing in Package, Operating Temperature Range, RoHS Status, SNR, Sampling Rate.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2157IUP-14#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2157CUP-14#TRPBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2156IUP-14
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$134.1 / Unit
View Datasheet →LTC2155IUP-14
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$107.04 / Unit
View Datasheet →LTC2157CUP-12
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$71.3 / Unit
View Datasheet →LTC2156CUP-14
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LTC2157CUP-14 Maximum Ratings & Electrical Characteristics
| Resolution | 14 bits |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate | 250 Msps per channel |
| Architecture | Pipelined |
| Input Type | Differential |
| Input Range | 1.5 Vp-p |
| Supply Voltage | 1.8 V (single) |
| Total Power Dissipation | 650 mW |
| SNR | 70 dB |
| SFDR | 90 dB |
| Full-Power Bandwidth (S/H) | 1.25 GHz |
| Digital Output | DDR LVDS |
| Reference | Internal or external |
| Configuration Interface | Serial SPI port |
| Package | 64-QFN (9 mm x 9 mm) with exposed pad |
| Pin/Package Code | UP (QFN-64) |
| Operating Temperature Range | 0C to +70C (commercial, C grade) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (PBF suffix) |
| Clock Duty Cycle Stabilizer | Optional, on-chip |
| Sleep/Nap Modes | Yes (low-power) |
LTC2157CUP-14 Pin Configuration
| Pin 1 | GND — Ground |
| Pin 2 | INA+ — Channel A positive differential analog input |
| Pin 3 | INA- — Channel A negative differential analog input |
| Pin 4 | VCM_A — Channel A common-mode voltage |
| Pin 5 | GND — Ground |
| Pin 6 | VREF — Voltage reference (internal or external) |
| Pin 7 | SENSE — Reference mode select |
| Pin 8 | GND — Ground |
| Pin 9 | INB+ — Channel B positive differential analog input |
| Pin 10 | INB- — Channel B negative differential analog input |
| Pin 11 | VCM_B — Channel B common-mode voltage |
| Pin 12 | GND — Ground |
| Pin 13 | CLK+ — Differential clock input positive |
| Pin 14 | CLK- — Differential clock input negative |
| Pin 15 | GND — Ground |
| Pin 16 | OE — Output enable (active high) |
| Pin 17 | GND — Ground |
| Pin 18 | NC — Not connected |
| Pin 19 | NC — Not connected |
| Pin 20 | GND — Ground |
| Pin 21 | OGND — Output logic ground |
| Pin 22 | OVDD — Output logic supply |
| Pin 23 | GND — Ground |
| Pin 24 | NC — Not connected |
| Pin 25 | NC — Not connected |
| Pin 26 | DA0+/DA0- — Channel A LVDS DDR data pair 0 |
| Pin 27 | DA1+/DA1- — Channel A LVDS DDR data pair 1 |
| Pin 28 | DA2+/DA2- — Channel A LVDS DDR data pair 2 |
| Pin 29 | DA3+/DA3- — Channel A LVDS DDR data pair 3 |
| Pin 30 | DA4+/DA4- — Channel A LVDS DDR data pair 4 |
| Pin 31 | DA5+/DA5- — Channel A LVDS DDR data pair 5 |
| Pin 32 | DA6+/DA6- — Channel A LVDS DDR data pair 6 |
| Pin 33 | GND — Ground |
| Pin 34 | DCO+/DCO- — DDR LVDS data clock output pair |
| Pin 35 | FR+/FR- — Frame clock output pair |
| Pin 36 | GND — Ground |
| Pin 37 | DB0+/DB0- — Channel B LVDS DDR data pair 0 |
| Pin 38 | DB1+/DB1- — Channel B LVDS DDR data pair 1 |
| Pin 39 | DB2+/DB2- — Channel B LVDS DDR data pair 2 |
| Pin 40 | DB3+/DB3- — Channel B LVDS DDR data pair 3 |
| Pin 41 | DB4+/DB4- — Channel B LVDS DDR data pair 4 |
| Pin 42 | DB5+/DB5- — Channel B LVDS DDR data pair 5 |
| Pin 43 | DB6+/DB6- — Channel B LVDS DDR data pair 6 |
| Pin 44 | GND — Ground |
| Pin 45 | SDO — SPI serial data output (open-drain) |
| Pin 46 | SDI — SPI serial data input |
| Pin 47 | SCK — SPI serial clock |
| Pin 48 | CS — SPI chip select (active low) |
| Pin 49 | RESET — Hardware reset (active low) |
| Pin 50 | PD — Power-down mode select |
| Pin 51 | NAP — Nap mode select |
| Pin 52 | GND — Ground |
| Pin 53 | VDD — 1.8 V analog supply |
| Pin 54 | GND — Ground |
| Pin 55 | VDD — 1.8 V analog supply |
| Pin 56 | GND — Ground |
| Pin 57 | VDD — 1.8 V analog supply |
| Pin 58 | GND — Ground |
| Pin 59 | VDD — 1.8 V analog supply |
| Pin 60 | GND — Ground |
| Pin 61 | VDD — 1.8 V analog supply |
| Pin 62 | GND — Ground |
| Pin 63 | VDD — 1.8 V analog supply |
| Pin 64 | EP — Exposed pad - thermal and electrical ground (must be soldered) |
Typical Applications
LTC2157CUP-14 is suitable for 6 applications: Software-Defined Radio (SDR) Receiver, MIMO LTE / WiMAX Transceiver Baseband, Multi-Channel Data Acquisition System, Medical Imaging Front-End (Ultrasound), Radar and Electronic Warfare Signal Processing, Test and Measurement Instrumentation.
Software-Defined Radio (SDR) Receiver
The LTC2157CUP-14 is well suited to software-defined radio receivers where dual simultaneous-sampling 14-bit channels digitize I/Q baseband or IF signals directly. The 250 Msps per-channel sample rate supports IF bandwidths up to approximately 100 MHz, while the 70 dB SNR and 90 dB SFDR preserve signal fidelity across the dynamic range required by modern digital demodulation. Differential inputs reject common-mode board noise, and DDR LVDS outputs feed directly into FPGAs such as Kintex or Cyclone families without level shifters. Low-power Sleep and Nap modes enable duty-cycled operation for battery-powered tactical or portable SDR platforms.
Recommended
MIMO LTE / WiMAX Transceiver Baseband
Multi-antenna MIMO LTE and WiMAX transceivers require multiple synchronized ADC channels per antenna branch. The LTC2157CUP-14 provides two simultaneous-sampling 14-bit channels at 250 Msps, allowing two diversity or polarization branches to be digitized by a single IC. The single 1.8 V supply simplifies baseband card power design, while the 650 mW dissipation keeps thermal rise manageable with a modest copper pour. Pin-compatible 12-bit and lower-speed LTC2156/2155 derivatives let designers scale BOM cost and power across product tiers without PCB rework.
Recommended
Multi-Channel Data Acquisition System
High-channel-count data acquisition systems benefit from the LTC2157CUP-14 dual-channel density: 32 such ICs deliver 64 simultaneous-sampling 250 Msps channels on a single backplane. The 1.25 GHz full-power sample-and-hold bandwidth preserves step-response fidelity for transient captures, while the 14-bit resolution satisfies 80 dB dynamic range requirements for vibration, acoustic, and ultrasonic test stands. The serial SPI configuration port allows per-channel gain and offset trim via a shared microcontroller, and the internal voltage reference eliminates a noise source in the analog front end.
Recommended
Medical Imaging Front-End (Ultrasound)
Portable and cart-based ultrasound imaging systems rely on dense ADC front-ends to digitize beamformed or pre-beamformed RF echoes. The LTC2157CUP-14 dual-channel architecture doubles the channel count per board while keeping 70 dB SNR adequate for B-mode and Doppler imaging. The 1.5 Vp-p easy-to-drive input range simplifies the LNA/HV-switch interface, and the 1.8 V single supply integrates with low-voltage FPGA SoCs. Optional duty-cycle stabilizer on the clock input compensates for non-50 percent clocks from FPGA PLLs, eliminating tone images at the carrier.
Recommended
Radar and Electronic Warfare Signal Processing
Phased-array radar and electronic-warfare receivers demand wide instantaneous bandwidth and high spurious-free dynamic range. The LTC2157CUP-14 captures 100 MHz-class IF signals with 90 dB SFDR, allowing small targets to be resolved in dense emitter environments. The dual channels support sum-and-difference or I/Q digitization in monopulse receivers, while Sleep/Nap modes reduce average dissipation in duty-cycled surveillance scans. The 64-QFN package's exposed pad couples to a copper ground pour for thermal stability under extended transmit/receive cycles.
Recommended
Test and Measurement Instrumentation
High-end oscilloscopes, spectrum analyzers, and arbitrary waveform digitizers leverage the LTC2157CUP-14's 1.25 GHz analog bandwidth and 250 Msps sample rate to deliver 100 MHz-class real-time capture on two channels per chip. The 14-bit resolution extends the dynamic range beyond traditional 8-bit instrument ADCs, supporting cleaner modulation analysis on RF test gear. The internal or external reference option allows precise gain calibration across the instrument's annual recalibration interval, and the SPI port exposes per-channel offset and gain trim for factory alignment.
Recommended
Recommended Products Summary
Engineering reference data for LTC2157CUP-14 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2157IUP-14#PBF | LTC2157CUP-14#TRPBF | LTC2156IUP-14 | LTC2155IUP-14 | LTC2157CUP-12 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (UP, 9x9 mm) | 64-QFN (UP, 9x9 mm) - same | 64-QFN (UP, 9x9 mm) - same | 64-QFN (UP, 9x9 mm) - same | 64-QFN (UP, 9x9 mm) - same | 64-QFN (UP, 9x9 mm) - same |
| Resolution | 14 bits | 14 bits | 14 bits | 14 bits | 14 bits | 12 bits |
| Sample Rate | 250 Msps | 250 Msps | 250 Msps | 210 Msps | 170 Msps | 250 Msps |
| Channels | 2 simultaneous sampling | 2 simultaneous sampling | 2 simultaneous sampling | 2 simultaneous sampling | 2 simultaneous sampling | 2 simultaneous sampling |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Operating Temperature | 0C to +70C (C grade) | -40C to +85C (I grade) | 0C to +70C (C grade) | -40C to +85C (I grade) | -40C to +85C (I grade) | 0C to +70C (C grade) |
Key Differentiators
- Simultaneous dual-channel sampling at 250 Msps with 14-bit resolution (vs LTC2156IUP-14)
- Highest SNR/SFDR pair in the LTC215x-14 family (vs LTC2155IUP-14)
- Industrial-temperature drop-in upgrade path (vs LTC2157IUP-14#PBF)
Design Notes
Estimated: drive the LTC2157CUP-14 differential analog inputs as a 100 ohm differential pair with length matching within 10 mil and characteristic impedance verified with a TDR or field-solver. Place the input traces on the top layer over a continuous ground plane and keep them isolated from the LVDS digital outputs by at least 200 mil to prevent digital noise coupling into the analog front end. Use an LTC6406 or similar low-noise differential driver if the source is single-ended.
Estimated: the 64-QFN (UP) package dissipates 650 mW under full dual-channel 250 Msps operation. With an estimated theta_JA of approximately 30 C/W on a 4-layer JEDEC test board, junction temperature rises roughly 20 C above ambient. For elevated ambient operation (>50 C) or full lifetime reliability, add a thermal via array directly under the exposed pad connecting to inner ground planes. Avoid placing the IC near other high-power components to minimize thermal gradient across the board.
Length-match each LVDS DDR output (DA0-DA6, DB0-DB6, DCO, FR) within 50 mil to preserve data-eye timing at the FPGA. Place a 100 ohm differential termination resistor across each LVDS pair at the receiver side. Maintain a continuous reference plane beneath LVDS traces and avoid crossing splits to prevent return-path discontinuities that degrade the data eye. The clock duty-cycle stabilizer should be enabled if the incoming CLK+/CLK- signal has a non-50 percent duty cycle.
Decouple each VDD pin with a 0.1 uF X7R ceramic capacitor placed within 3 mm of the pin and a single 10 uF bulk capacitor near the IC. The OVDD (output logic supply) is typically tied to the FPGA I/O voltage (1.8 V or 2.5 V) and should be filtered separately from the analog VDD to prevent digital switching noise from corrupting the analog supply. Use a ferrite bead between analog and digital 1.8 V rails if noise coupling is observed.
Do not float the SENSE pin - tie it to GND for internal reference mode or to VDD for external reference mode. Leave unused LVDS data pairs (if the application uses fewer bits) terminated with 100 ohm differential resistors rather than left open. The exposed pad must be soldered to the PCB ground plane for thermal dissipation and electrical reference; a non-soldered exposed pad will trigger thermal-shutdown behavior at lower ambient temperatures.
Compliance Information
PBF suffix confirms lead-free and RoHS-compliant finish. Halogen-free status not stated in the verified web data. AEC-Q100 not applicable (this is a commercial-grade high-speed ADC).
