PN7161B1HN-C100Y - NFC Controller with NCI Interface | NXP
MPN: PN7161B1HN-C100Y ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.85 | $5.85 |
| 10 | $5.27 | $52.70 |
| 100 | $4.69 | $469.00 |
| 500 | $4.21 | $2,105.00 |
| 1,000 | $3.74 | $3,740.00 |
PN7161B1HN-C100Y Overview
What is an NFC controller? An NFC (Near Field Communication) controller is a specialized mixed-signal IC that handles the 13.56 MHz RF physical layer and the NFCIP-1, NFCIP-2, ISO 14443, ISO 15693, FeliCa, and MIFARE protocol stacks, exposing a standardized host interface (NCI, NCI 2.0) to the application processor. In the system hierarchy, an NFC controller sits between the RF antenna and the host CPU and belongs to the broader category of short-range wireless ICs within RF & wireless semiconductor products.
Key features include integrated RF front-end with automatic antenna tuning support, full NFC Forum tag type and peer-to-peer mode support, EMVCo L1 and L2 stack offload, dynamic load modulation for Apple ECP, low-power standby modes, and an integrated LDO for the RF section. The PN7161 builds on the PN7160 by adding Apple ECP enablement after formal authorization, while keeping the same VQFN-40 footprint and pinout.
The device architecture combines an ARM Cortex-M0 core for firmware execution with hardware accelerators for framing, crypto, and EMVCo polling loops. A high-efficiency RF transmitter uses a single-ended output driving an external EMC filter and matching network, while a pair of differential Rx inputs accept the tag/NFC device response. An integrated temperature sensor and battery-friendly deep-sleep modes reduce idle consumption below typical NFC reader IC benchmarks.
Typical applications include NFC payment terminals (POS), mobile point-of-sale accessories, EMV contactless readers, access control and ticketing readers, NFC-enabled IoT gateways, and automotive digital key / wireless charging authentication modules. The wide host-side voltage range also makes it suitable for direct connection to 1.8 V application processors.
When designing with this device, allocate at least 4 layers of the PCB to the RF section and follow the NXP antenna design guide for the matching network and EMC low-pass filter. A stable host supply and a clean reset sequence are required during firmware download and after EMV stack updates.
This page consolidates distributor pricing, drop-in NXP same-family alternatives, and application-specific design notes that complement the manufacturer datasheet and the NXP NFC forum reference designs.
Drop-in alternatives for PN7161B1HN-C100Y — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with PN7161B1HN-C100Y (same form factor and footprint) — differing in Host Interface, Package, Peak Reflow Temperature, Supported Protocols, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
PN7161A1HN
✅ Drop-In✓ In Stock
$4.72 / Unit
View Datasheet →PN7160A1HN
✅ Drop-In✓ In Stock
$2.15 / Unit
View Datasheet →PN7160B1HN/C100Y
✅ Drop-In📋 Reference alternative (not in catalog)
PN7161B1HN/C100E
✅ Drop-In📋 Reference alternative (not in catalog)
PN7161B1HN/C100YTR
✅ Drop-In📋 Reference alternative (not in catalog)
PN7160B1HN/C100E
✅ Drop-In📋 Reference alternative (not in catalog)
PN7161B1HN-C100Y Specifications
| Function | NFC Controller with NCI interface |
| RF Frequency | 13.56 MHz |
| Supported Standards | FeliCa, ISO 14443, ISO 15693, MIFARE, NFC Forum, EMVCo |
| Host Interface | SPI (NCI) |
| Supply Voltage (VDD) | 1.65 V to 1.95 V |
| Supply Voltage (VBAT/VIN) | 3.0 V to 3.6 V |
| Package | 40-VFQFN Exposed Pad (HVQFN-40, 6 mm x 6 mm) |
| Mounting Type | Surface Mount |
| Moisture Sensitivity Level (MSL) | 3 |
| Peak Reflow Temperature | 260 C |
| Operating Temperature | -40 C to +85 C |
| EMVCo Compliance | EMV L1 compliant |
| Apple ECP Support | Yes (after formal authorization) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
| Protocol | NFCIP-1, NFCIP-2 |
| Antenna Outputs | Single-ended TX, differential RX |
| Integrated LDO | Yes (RF supply) |
PN7161B1HN-C100Y Pin Configuration
| Pin 1 | VDD — Host supply voltage (1.65 V to 1.95 V) |
| Pin 2 | GND — Ground reference |
| Pin 3 | VBAT — Battery supply voltage (3.0 V to 3.6 V) |
| Pin 4 | ANT1 — Antenna output to matching network (single-ended TX) |
| Pin 5 | ANT2 — Antenna output return path |
| Pin 6 | RXP — Differential receiver positive input |
| Pin 7 | RXN — Differential receiver negative input |
| Pin 8 | SCLK — SPI host clock input |
| Pin 9 | MOSI — SPI host data input (master out, slave in) |
| Pin 10 | MISO — SPI host data output (master in, slave out) |
| Pin 11 | NIRQ — Host interrupt request (active low) |
| Pin 12 | NRESET — Reset input (active low) |
| Pin 13 | SPI_PWR — SPI host power domain reference |
| Pin 14 | GPIO1 — General purpose IO / LED drive |
| Pin 15 | GPIO2 — General purpose IO |
| Pin 16 | GPIO3 — General purpose IO |
| Pin 17 | GPIO4 — General purpose IO |
| Pin 18 | GPIO5 — General purpose IO |
| Pin 19 | GPIO6 — General purpose IO |
| Pin 20 | GPIO7 — General purpose IO |
| Pin 21 | GPIO8 — General purpose IO |
| Pin 22 | XTAL1 — Crystal oscillator input |
| Pin 23 | XTAL2 — Crystal oscillator output |
| Pin 24 | CLK_OUT — Reference clock output |
| Pin 25 | PMU_OUT — Internal LDO output (RF supply) |
| Pin 26 | AUX_1 — Auxiliary analog pin |
| Pin 27 | AUX_2 — Auxiliary analog pin |
| Pin 28 | TEST — Factory test pin (must be left open in application) |
| Pin 29 | NC — Not connected (per datasheet) |
| Pin 30 | NC — Not connected (per datasheet) |
| Pin 31 | NC — Not connected (per datasheet) |
| Pin 32 | NC — Not connected (per datasheet) |
| Pin 33 | NC — Not connected (per datasheet) |
| Pin 34 | NC — Not connected (per datasheet) |
| Pin 35 | NC — Not connected (per datasheet) |
| Pin 36 | NC — Not connected (per datasheet) |
| Pin 37 | NC — Not connected (per datasheet) |
| Pin 38 | NC — Not connected (per datasheet) |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | NC — Not connected (per datasheet) |
Typical Applications
PN7161B1HN-C100Y is suitable for 6 applications: EMV Contactless Payment Terminal (POS), Mobile Point-of-Sale (mPOS) Accessory, Access Control and Ticketing Reader, NFC-Enabled IoT Gateway and Pairing Hub, Automotive Digital Key Reader, Industrial NFC Tag Programming Station.
EMV Contactless Payment Terminal (POS)
The PN7161B1HN-C100Y is purpose-built for EMV contactless payment terminals where EMVCo L1 compliance is mandatory. The integrated EMV polling loop offloads the host processor from real-time RF framing, while 13.56 MHz support for ISO 14443 Type A/B and FeliCa covers global contactless card standards. The SPI host interface enables low-latency APDU exchange with secure elements over NCI, and Apple ECP support (after authorization) keeps the design ready for Apple Pay VAS extensions without a hardware swap.
Recommended
Mobile Point-of-Sale (mPOS) Accessory
Battery-powered mPOS card readers benefit from the PN7161B1HN-C100Y's wide 3.0 V to 3.6 V VBAT supply range and deep-sleep current profile. The 40-pin HVQFN-40 package is small enough to fit into a smartphone dongle form factor, while the SPI interface allows direct connection to a low-cost MCU host without needing a high-speed bus. Integrated dynamic load modulation for Apple ECP ensures compatibility with iPhone-based tap-to-pay scenarios common in retail.
Recommended
Access Control and Ticketing Reader
The PN7161B1HN-C100Y supports ISO 14443, ISO 15693, FeliCa, and MIFARE protocols needed for unified access control, transit ticketing, and corporate badge readers. The single-ended TX output drives a matching network tuned for typical 13.56 MHz antennas embedded in turnstile or wall readers, while differential RX inputs preserve signal integrity over longer antenna cables. EMV L1 compliance means the same hardware can also accept contactless bank cards, simplifying multi-application deployments.
Recommended
NFC-Enabled IoT Gateway and Pairing Hub
IoT gateways can use the PN7161B1HN-C100Y as an NFC commissioning and pairing interface for Wi-Fi or Bluetooth credentials from a user's phone. The NCI 2.0 host interface simplifies integration with Linux-based gateways, and NFC Forum tag read/write support allows diagnostic NFC tags to be provisioned in the field. The 1.65 V to 1.95 V VDD rail is directly compatible with 1.8 V application processors used in modern IoT SoCs, eliminating level shifters.
Recommended
Automotive Digital Key Reader
Automotive digital key and wireless charging authentication modules leverage the PN7161B1HN-C100Y's NFCIP-1 peer-to-peer mode to communicate with phones acting as car keys. Apple ECP support (after authorization) is required for iPhone-based digital key, while the EMV L1 stack handles secure transactions for in-cabin payment use cases. The -40 C to +85 C operating temperature range and the HVQFN-40 thermal pad support reliable operation in cabin and door-handle environments.
Recommended
Industrial NFC Tag Programming Station
Manufacturing test stations and industrial NFC tag programmers use the PN7161B1HN-C100Y's high RF output power and reliable ISO 15693 long-range read capability to program and verify tags at production speeds. The SPI host interface allows deterministic timing control by an MCU-based station controller, and the exposed pad ensures continuous duty cycle operation without thermal throttling. EMVCo stack reuse enables optional payment-tag certification within the same firmware image.
Recommended
Recommended Products Summary
Engineering reference data for PN7161B1HN-C100Y — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | PN7161A1HN | PN7160A1HN | PN7160B1HN/C100Y | PN7161B1HN/C100E | PN7161B1HN/C100YTR | PN7160B1HN/C100E |
|---|---|---|---|---|---|---|---|
| Package | 40-VFQFN Exposed Pad (HVQFN-40, 6x6 mm) | 40-VFQFN Exposed Pad - same | 40-VFQFN Exposed Pad - same | 40-VFQFN Exposed Pad - same | 40-VFQFN Exposed Pad - same | 40-VFQFN Exposed Pad - same | 40-VFQFN Exposed Pad - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| RF Frequency | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz |
| Host Interface | SPI (NCI) | Plug-and-play (NCI) | Plug-and-play (NCI) | SPI (NCI) | SPI variant (NCI) | SPI (NCI) | SPI variant (NCI) |
| Apple ECP Support | Yes (after authorization) | Yes (after authorization) | No | No | Yes (after authorization) | Yes (after authorization) | No |
| EMV L1 Compliant | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| Supported Standards | FeliCa, ISO 14443, ISO 15693, MIFARE, NFC | FeliCa, ISO 14443, ISO 15693, MIFARE, NFC | FeliCa, ISO 14443, ISO 15693, MIFARE, NFC | FeliCa, ISO 14443, ISO 15693, MIFARE, NFC | FeliCa, ISO 14443, ISO 15693, MIFARE, NFC | FeliCa, ISO 14443, ISO 15693, MIFARE, NFC | FeliCa, ISO 14443, ISO 15693, MIFARE, NFC |
| Supply Voltage | 1.65 V to 1.95 V (VDD), 3.0 V to 3.6 V (VBAT) | 1.65 V to 1.95 V, 3.0 V to 3.6 V | 1.65 V to 1.95 V, 3.0 V to 3.6 V | 1.65 V to 1.95 V, 3.0 V to 3.6 V | 1.65 V to 1.95 V, 3.0 V to 3.6 V | 1.65 V to 1.95 V, 3.0 V to 3.6 V | 1.65 V to 1.95 V, 3.0 V to 3.6 V |
| MSL Level | 3 | 3 | 3 | 3 | 3 | 3 | 3 |
Key Differentiators
- Apple ECP firmware enablement after authorization (vs PN7160B1HN/C100Y)
- C100Y SPI-specific firmware image (vs PN7161A1HN)
- Wide dual-rail supply design (vs PN7160A1HC)
- EMV L1 compliance on-silicon (vs PN7150B0HN)
Design Notes
Route the antenna traces over a continuous ground plane reference and use coplanar waveguide with ground (CPWG) for the 13.56 MHz RF path from ANT1/ANT2 to the EMC low-pass filter. According to NXP antenna design guides, the matching network must be placed as close as possible to the ANT pins, and the EMC low-pass filter (typically 470 nH inductors + 47 pF capacitors) must be within 5 mm of the IC to suppress harmonics and meet regulatory limits.
Decouple VBAT with a 10 uF bulk capacitor and a 100 nF ceramic placed within 2 mm of the VBAT pin, and decouple VDD with a 1 uF X7R ceramic within 2 mm of the VDD pin. According to the NXP PN7160/PN7161 datasheet, the integrated LDO requires a stable VBAT input above 3.0 V for the RF section to maintain regulation during high-current EMVCo polling pulses, which can transiently draw hundreds of mA.
Do not omit the external 27.12 MHz crystal load capacitors; use NXP-recommended 12 pF C0G/NP0 types to stay within the PN7161B1HN-C100Y clock accuracy budget. According to the NXP PN7160/PN7161 datasheet, clock frequency drift above +/-50 ppm can break FeliCa and EMVCo carrier-frequency windows, causing reader failures that look like software bugs. Always perform a NXP-recommended cold-start reset sequence after VBAT power-up before issuing NCI commands.
Solder the central exposed pad of the HVQFN-40 to a ground copper pour of at least 25 mm squared across inner PCB layers with thermal vias on a 1 mm pitch. Estimated: at full RF output power during continuous EMV polling, power dissipation reaches approximately 0.3 W; without the EPAD land pattern the junction temperature can rise 30-40 C above ambient, potentially triggering thermal shutdown in enclosed enclosures.
Keep the SPI bus traces under 50 mm and add 33 ohm series termination at the host MCU side if the bus length approaches that limit. According to the NXP PN7160/PN7161 datasheet, SPI clock rates up to 15 MHz are supported but signal-integrity issues typically appear first as NCI timeout errors rather than SPI protocol faults, so route the SPI_PWR reference pin with the bus to provide a clean return path.
Compliance Information
RoHS and REACH compliance per NXP product page. Not AEC-Q100 qualified; this part targets consumer payment/IoT applications rather than automotive. Lead-free reflow profile compatible with 260 C peak per JEDEC J-STD-020.
