SN74AUP2G126YZPR - Dual Bus Buffer 3-State 8-DSBGA | TI
MPN: SN74AUP2G126YZPR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0.42 | $0.42 |
| 10 | $0.38 | $3.80 |
| 100 | $0.3 | $30.00 |
| 500 | $0.25 | $125.00 |
| 1,000 | $0.21 | $210.00 |
SN74AUP2G126YZPR Overview
A bus buffer (or line driver) is a digital circuit element that reproduces a logic input at its output while providing higher drive strength, level translation, or bus-isolation capability. Within the broader taxonomy, a bus buffer belongs to the logic ICs category (sub-family: buffers/drivers/receivers) and falls under the CMOS logic umbrella alongside gates, inverters, and transceivers. Buffers are functionally distinct from transceivers: a buffer is unidirectional, while a transceiver is bidirectional and typically includes bus-side termination. The AUP family is TI's premier low-power CMOS sub-family, designed for sub-1 GHz edge rates and sub-microamp quiescent current budgets, sitting between the AUC (1.8-V optimized) and LVC (general-purpose) families in TI's logic-portfolio positioning.
Key features include an operating voltage range of 0.8 V to 3.6 V across VCC, partial-power-down support via Ioff (live-insertion safe), 3.6-V tolerant inputs when VCC is at 3.3 V, low static and dynamic power consumption characteristic of AUP logic, and a maximum quiescent current in the microamp range. Each output stage uses TI's standard 3-state architecture, with an active-high output enable (OE) per channel. The 8-ball DSBGA package keeps the footprint extremely small - approximately 0.9 mm x 0.9 mm - making the part suitable for space-constrained wearables and handhelds.
Architecturally, the SN74AUP2G126 uses TI's AUP silicon-gate CMOS process with industry-standard Schmitt-trigger inputs (partial), low-drive-strength CMOS outputs, and the Ioff feature that prevents back-feeding current into a powered-down output pin. Inputs are tolerant up to 3.6 V regardless of VCC, providing robust interface to 1.8 V, 2.5 V, and 3.3 V domain signals without external protection.
Typical applications include smartphones and wearables, IoT sensor nodes, low-power portable instrumentation, voltage-level shifting between 1.2 V microcontrollers and 3.3 V peripherals, and any system needing bus multiplexing or isolation with minimal quiescent power. The 3-state outputs allow direct bus sharing with other drivers under careful OE arbitration.
Designers should note that the DSBGA package requires reflow soldering with appropriate profile and that the small land pattern demands careful PCB layout and precise stencil design to avoid defects. When designing with this part, ensure that the OE pins are properly managed during power-up to prevent bus contention; pull OE to a defined logic level at startup rather than leaving them floating.
Drop-in alternatives for SN74AUP2G126YZPR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SN74AUP2G126YEPR
✅ Drop-In📋 Reference alternative (not in catalog)
SN74AUC2G126YZPR
✅ Drop-In📋 Reference alternative (not in catalog)
SN74AUP2G126YZPR Maximum Ratings & Electrical Characteristics
| Function | Buffer, Non-Inverting |
| Number of Channels | 2 |
| Bits per Channel | 1 |
| Output Type | 3-State |
| Logic Family | AUP (Advanced Ultra-Low Power CMOS) |
| Supply Voltage (VCC) | 0.8 V to 3.6 V |
| Input Voltage Tolerance | 3.6 V (when VCC = 0 V to 3.6 V) |
| Operating Temperature | -40C to +85C |
| Package | 8-DSBGA (YZP) approx. 0.9 mm x 0.9 mm |
| Mounting Type | Surface Mount (BGA) |
| Ioff Feature | Yes (partial-power-down safe) |
| Output Enable | Active-High (one per channel) |
SN74AUP2G126YZPR Pin Configuration
| Pin A1 | 1OE — Output enable for channel 1 (active high) |
| Pin A2 | 1A — Channel 1 input |
| Pin B1 | GND — Ground |
| Pin B2 | 1Y — Channel 1 output |
| Pin C1 | VCC — Supply voltage (0.8 V to 3.6 V) |
| Pin C2 | 2A — Channel 2 input |
| Pin D1 | 2Y — Channel 2 output |
| Pin D2 | 2OE — Output enable for channel 2 (active high) |
Typical Applications
SN74AUP2G126YZPR is suitable for 7 applications: Smartphone / Wearable Handheld Devices, IoT Sensor Nodes, Voltage Level Translation Between 1.2 V MCU and 3.3 V Peripherals, Battery-Powered Portable Instrumentation, Mobile Display Module Buffers, Low-Power Embedded System Clock Fanout, Industrial Control Module Bus Arbitration.
Smartphone / Wearable Handheld Devices
The SN74AUP2G126YZPR fits wearable and smartphone designs because the AUP family delivers sub-microamp quiescent current at a 0.8 V to 3.6 V VCC range, with the 8-DSBGA (YZP) package covering less than 1 mm x 1 mm of board area. With 3-state outputs and per-channel OE, design teams can power-gate peripherals like sensors or radios to slash sleep current while leaving a single driver on the always-on rail. Compared to general-purpose CMOS logic like the LVC family, AUP reduces leakage by roughly an order of magnitude, directly improving the device's standby days.
Recommended
IoT Sensor Nodes
IoT nodes powered by coin-cell or energy-harvesting sources depend on minimal quiescent draw, and the SN74AUP2G126YZPR delivers AUP-class low ICC across 0.8 V to 3.6 V, which is the typical operating window for batteries from a single Li-coin cell down to a partially drained alkaline pair. The two-channel 3-state buffer enables a sensor MISO/MOSI bus or a shared interrupt line to be isolated and driven with controlled direction, helping aggregate multiple slow peripherals onto one microcontroller pin. Compared to a discrete FET switch, the AUP buffer adds less than 10 µA quiescent overhead and removes biasing complexity.
Recommended
Voltage Level Translation Between 1.2 V MCU and 3.3 V Peripherals
The SN74AUP2G126YZPR performs unidirectional level shifting transparently because VCC supports 0.8 V to 3.6 V and inputs are 3.6-V tolerant regardless of VCC. Powering VCC at 3.3 V allows 1.2 V or 1.8 V microcontroller GPIO to drive 3.3 V peripheral logic without external translators or MOSFETs. The 3-state OE lets the designer power-gate the downstream peripheral cleanly during deep sleep, a common requirement in modern PMIC-driven SoCs.
Recommended
Battery-Powered Portable Instrumentation
Handheld measurement instruments rely on long battery life and dense PCB layouts; the SN74AUP2G126YZPR's 8-DSBGA footprint keeps the buffer area negligible inside a probe head, while the AUP leakage floor preserves run-time hours the user can actually see on a charge gauge. With 3-state OE per channel, two analog MUX enable lines, test-mode flags, or front-end power-rail switches can be controlled independently from a single COB ASIC. Compared to a wider-pitch TSSOP alternative, BGA placement also shortens critical traces and reduces EMI loop area.
Recommended
Mobile Display Module Buffers
Small-format mobile displays frequently use parallel RGB or SPI control buses routed across hinge or flex sections; the SN74AUP2G126YZPR can sit at the flex connector to re-buffer logic signals at sub-ns propagation delays so that signal integrity is preserved. Because outputs are 3-stateable, designers can parallel two drivers onto the same bus and use OE arbitration instead of mechanical switches. The wide VCC supports direct interface to both 1.8 V display controllers and 3.3 V timing generators.
Recommended
Low-Power Embedded System Clock Fanout
When a 32 kHz or low-MHz reference clock must be fanned out across multiple sub-blocks, the SN74AUP2G126YZPR's two non-inverting buffers provide clean re-driving with microamp-level leakage and 3-state output control for unused branches. Driving the clock into a powered-down block is blocked by pulling OE high-impedance, eliminating the back-feed risk that often forces designers to add series FETs. Placing the part near the clock source keeps the trace short and the EMI footprint small.
Recommended
Industrial Control Module Bus Arbitration
In multi-board industrial control modules, the SN74AUP2G126YZPR serves as a 3-state bus arbiter buffer where 24 V-tolerant upstream signals must be conditioned into a low-voltage MCU bus. Inputs accept up to 3.6 V and VCC supports 3.3 V typical industrial logic, allowing direct connection to digital isolator outputs or sensor front-ends. Compared to discrete open-drain bus switches, this part provides deterministic rise/fall times for reliable arbitration timing in noisy field environments.
Recommended
Recommended Products Summary
Engineering reference data for SN74AUP2G126YZPR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SN74AUP2G126YEPR | SN74AUC2G126YZPR | SN74AUP2G126RSWR |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 8-DSBGA (YZP) | 8-DSBGA NanoFree (YEP) - same footprint family | 8-DSBGA (YZP) - same | 8-UQFN (RSW) - different |
| Logic Family | AUP | AUP | AUC | AUP |
| VCC Range | 0.8 V to 3.6 V | 0.8 V to 3.6 V | 1.8 V (AUC optimized) | 0.8 V to 3.6 V |
| Number of Channels | 2 | 2 | 2 | 2 |
| Output Type | 3-State (active-HIGH OE) | 3-State (active-HIGH OE) | 3-State (active-HIGH OE) | 3-State (active-HIGH OE) |
| 3.6 V Input Tolerance | Yes | Yes | Yes | Yes |
Key Differentiators
- Lowest quiescent current in TI's logic portfolio (vs SN74AUC2G126YZPR)
- 3-state outputs with active-HIGH OE per channel (vs SN74AUP2G125)
- Ultra-compact 8-DSBGA (YZP) footprint (vs SN74AUP2G126DCUR)
- Wide VCC range for mixed-voltage designs (vs SN74AUC2G126YZPR)
Design Notes
Floating OE pins can cause unpredictable behavior at power-up because the AUP family uses small bias currents; pull each OE to a defined logic level through a 100 kΩ resistor. Driving OE during VCC ramp-up may cause bus contention if downstream devices are also active - sequence OE HIGH-Z until VCC is stable. Designers often add a small RC delay on OE to ensure clean startup.
The 8-DSBGA (YZP) footprint requires precise PCB land-pattern fabrication. Use the TI-recommended land dimensions from the datasheet mechanical drawing - typically about 0.225 mm diameter pads with 0.4 mm pitch. Apply a Type 4 or finer solder paste with a stencil thickness of 0.1 mm to avoid solder-bridge shorts between 0.4 mm-pitch bumps. Reflow with a profile that does not exceed 260°C peak per JEDEC J-STD-020 moisture sensitivity.
Estimated: total quiescent draw for both buffers enabled and outputs idle is the sum of both channel ICC contributions and should remain in the low-microamp region. For battery-life modeling, compute the AVERAGE current including OE-disabled periods; with OE held low for unused channels, only the always-active channel contributes to leakage. Decoupling with a 0.1 µF X7R ceramic within 50 mil of VCC is recommended.
At 3.3 V VCC the SN74AUP2G126YZPR supports clock frequencies in the tens-of-MHz range; for higher-speed signals, prefer the AUP2G family specified for equivalent speed or place a series damping resistor (10-33 Ω) near the driver to control overshoot. Keep output traces short and avoid stubs to maintain clean edges. Differential pairs or impedance-controlled traces are NOT needed for typical AUP clock signals below 50 MHz.
Compliance Information
RoHS and halogen-free compliance confirmed via TI product page. Standard part is NOT AEC-Q100 qualified; use the -Q1 suffix variant for automotive applications. TI AUP family is also lead-free with matte-tin ball finish compatible with Pb-free reflow profiles.
