UCD90160ARGCT - 16-Rail PMBus Sequencer & Monitor | Texas Instruments
MPN: UCD90160ARGCT ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.24 | $12.24 |
| 10 | $11.05 | $110.50 |
| 100 | $9.78 | $978.00 |
| 500 | $8.82 | $4,410.00 |
| 1,000 | $7.95 | $7,950.00 |
UCD90160ARGCT Overview
A power supply sequencer is a programmable controller that supervises the turn-on and turn-off order, voltage margin, and fault response of multiple DC rails in a complex system such as a server, FPGA SoM, or ATX-class board. By centralizing rail sequencing in one IC rather than discrete reset supervisors, designers replace glue logic, RC delay chains, and multiple supervisor ICs with one PMBus-programmable device, simplifying BOM and improving diagnostic visibility through the integrated system health telemetry interface.
Key features include sequence control based on time, rail-dependency, and pin-dependency, ACPI support for desktop power-button S0/S3/S5 state coordination, a 100-pin-compatible scalable family (UCD90120A / UCD90124A / UCD90910 / UCD90160), and integration with the TI Fusion Digital Power Designer GUI. Black-box fault logging, margining, and closed-loop trim of downstream DC/DC converters are standard capabilities supported through the PMBus command set.
The device integrates a 12-bit ADC and precision reference, fault-logging non-volatile memory, programmable GPIOs for PERST#, ENABLE, and PG_OUT behavior, and a JTAG/I2C/PMBus host interface. The architecture follows the UCD90xxx family: an embedded microcontroller runs sequencing state machines while a dedicated ADC front-end maintains 400 µs rail sampling independent of host interaction. The result is deterministic rail sequencing even when the system host is stalled during fault recovery.
Typical applications include ATX/Server power sequencing for multi-rail processors, FPGA and SoC power-up coordination, industrial and telecommunications equipment with hot-swap controllers, and automated test platforms that require precise rail ordering and margin verification. ACPI support makes the part particularly natural in x86 system designs that need S3 suspend/resume state transitions.
When designing with this device, plan for a 3.3 V auxiliary rail present at all times because the sequencer must remain alive before the main rails come up. Place the decoupling capacitor network (1 µF + 0.1 µF) within 5 mm of the AVDD pin and follow TI's RGC PCB layout guideline in the EVM user's guide to keep ADC readings clean across all 16 channels.
This page synthesizes distributor pricing, drop-in cross-reference parts, and practical layout notes compiled from the manufacturer datasheet and TI EVM user's guide so engineers can quickly qualify the UCD90160ARGCT against alternative sequencers in the same package family.
Drop-in alternatives for UCD90160ARGCT — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
UCD90160ARGCR
✅ Drop-In📋 Reference alternative (not in catalog)
UCD90910ARGCT
✅ Drop-In📋 Reference alternative (not in catalog)
UCD90124ARGCT
✅ Drop-In📋 Reference alternative (not in catalog)
UCD90120ARGCR
✅ Drop-In📋 Reference alternative (not in catalog)
UCD90120AARGCT
✅ Drop-In📋 Reference alternative (not in catalog)
UCD90160ARGCT Specifications
| Function | 16-Rail PMBus Power Supply Sequencer and System Health Monitor |
| Number of Monitored Rails | 16 |
| Number of Sequenced Outputs | 16 |
| Rail Sampling Interval | 400 µs (all rails) |
| ADC Resolution | 12-bit |
| Internal Voltage Reference | 2.5 V, 0.5% |
| Programmable Thresholds per Rail | 4 (UV + OV) |
| Supply Voltage Range | 3 V to 3.6 V |
| Quiescent Current (typ) | 50 mA |
| Host Interface | PMBus / I2C |
| ACPI Support | Yes (S0 / S3 / S5) |
| Sequencing Dependencies | Time, Rail, Pin |
| Operating Temperature Range | -40 °C to +125 °C |
| Package | VQFN-64 (RGC) 9x9 mm with exposed pad |
| Mounting Type | Surface Mount |
| MSL Level | Level-3 (per JEDEC J-STD-020) |
| RoHS Status | Compliant |
| Margin / Trim Support | Yes (PMBus) |
| Fault Black-Box Logging | Yes (non-volatile) |
| Family Pin Compatibility | UCD90120A / UCD90124A / UCD90910 / UCD90160 |
UCD90160ARGCT vqfn-64 (rgc) 9x9 mm with exposed pad Pin Configuration Guide
Pin configuration for UCD90160ARGCT (vqfn-64 (rgc) 9x9 mm with exposed pad package). Pin numbering, functions, and connection diagrams are defined in the manufacturer datasheet. Refer to it for the exact footprint and soldering guidelines.
No detailed pinout data available for UCD90160ARGCT.
Refer to the datasheet for full pin configuration.
Typical Applications
UCD90160ARGCT is suitable for 6 applications: ATX Server Power Sequencing, FPGA SoC Multi-Rail Power-Up Coordination, Telecom / Industrial Equipment with Hot-Swap, Automated Test Equipment (ATE) Rails, Storage Controller / RAID Card, Workstation Graphics and ASIC Boards.
ATX Server Power Sequencing
The UCD90160ARGCT sequences the 3.3 V standby, 5 V, 12 V, and multi-phase core rails of an ATX-class server board in a deterministic S0/S3/S5 order. Its 16 monitored rails with 400 µs sampling catch undervoltage or overvoltage faults on the CPU VCORE, memory VTT, and PCH rails within one cycle of the 1.2 V reference, enabling clean Intel VR12.5/12.9 turn-on coordination. Compared with a discrete supervisor chain, the device cuts BOM count by ~10 chips and exposes rail health over PMBus for BMC telemetry.
Recommended
FPGA SoC Multi-Rail Power-Up Coordination
FPGA SoC boards such as Kintex-7, Zynq UltraScale, and Stratix-10 require sequenced VCCINT, VCCAUX, MGTAVCC, and MGTRAVCC power-up with strict dependency rules. The UCD90160ARGCT supports sequence dependencies on time, rail, and GPIO pin, allowing the FPGA's PWRMGMT pin to release PERST# only after every rail is within margin. Its non-volatile fault black-box stores the last event before a brown-out so field-failure analysis is straightforward.
Recommended
Telecom / Industrial Equipment with Hot-Swap
In -48 V telecom shelves and industrial DIN-rail systems, the UCD90160ARGCT monitors backplane rails presented by hot-swap controllers and arbitrates the turn-on sequence for downstream DC/DC converters. Rail-sampling at 400 µs ensures that an over-voltage on a backplane feed triggers a sequenced shutdown rather than a hard fault. ACPI support is optional here but the device's programmable GPIOs provide PERST# coordination with the board management controller (BMC).
Recommended
Automated Test Equipment (ATE) Rails
Production ATE systems require identical power-up order across thousands of test cycles with margin trim to verify DUT margins. The UCD90160ARGCT's PMBus MARGIN command dynamically trims each rail to ±5% of nominal without re-routing the test fixture, and the 12-bit ADC verifies the actual settled voltage within 0.5% reference accuracy. Programmable fault-response rules let the sequencer re-sequence within milliseconds after a transient drop, maximizing tester throughput.
Recommended
Storage Controller / RAID Card
SAS/SATA RAID controllers, NVMe SSDs, and HDD backplanes rely on a deterministic 5 V/12 V/3.3 V turn-on order before the host initiates PCI Express link training. The UCD90160ARGCT sequences the PCIe slot power and asserts PWR_OK to the BMC after all monitored rails are in regulation. Its 16-channel capacity leaves headroom for individual drive bay supervision on enterprise JBOD chassis.
Recommended
Workstation Graphics and ASIC Boards
GPU compute cards and ASIC accelerator boards need tightly coordinated VCORE, VMEM, VDDCI, and PEX rails with PG (power-good) feedback. The UCD90160ARGCT sequences rails based on PG inputs from upstream converters, asserts PWRGOOD to the host GPU, and logs the last rail state if a fault occurs during training. ACPI support is also valuable on workstation cards used in S3 sleep scenarios on Tower chassis.
Recommended
Recommended Products Summary
Engineering reference data for UCD90160ARGCT — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | UCD90160ARGCR | UCD90910ARGCT | UCD90124ARGCT | UCD90120ARGCR | UCD90120AARGCT |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | VQFN-64 (RGC) 9x9 mm | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same |
| Monitored / Sequenced Rails | 16 / 16 | 16 / 16 | 12 / 12 | 8 / 8 | 12 / 12 | 12 / 12 |
| Supply Voltage | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V |
| Quiescent Current (typ) | 50 mA | 50 mA | 40 mA | 30 mA | 40 mA | 40 mA |
| ACPI Support | Yes | Yes | Yes | No | No | No |
| Internal VREF | 2.5 V, 0.5% | 2.5 V, 0.5% | 2.5 V, 0.5% | 2.5 V, 1% | 2.5 V, 1% | 2.5 V, 0.5% |
| Operating Temperature | -40 °C to +125 °C | -40 °C to +125 °C | -40 °C to +125 °C | -40 °C to +125 °C | -40 °C to +125 °C | -40 °C to +125 °C |
| Reel Quantity (suffix) | T = 250 pcs | R = 2500 pcs | T = 250 pcs | T = 250 pcs | R = 2500 pcs | T = 250 pcs |
Key Differentiators
- 16 monitored rails plus ACPI in the same VQFN-64 package (vs UCD90910ARGCT)
- Higher channel count at the same factory reel (vs UCD90160ARGCR)
- Tightest ADC VREF accuracy in the UCD90xxx family (vs UCD90124ARGCT)
Design Notes
The UCD90160ARGCT's AVDD (3.3 V auxiliary) must be present before all sequenced rails come up. Source it from the ATX 5Vsb or a dedicated standby regulator and add 1 µF + 0.1 µF decoupling within 5 mm of the AVDD pin. Brown-out detection on the sequenced rails is sensitive to voltage droop, so keep the AVDD ripple under 30 mVpk-pk to avoid spurious fault interrupts.
Estimated: with 50 mA quiescent current and 3.3 V supply, the UCD90160ARGCT dissipates roughly 165 mW. On the RGC 9x9 mm package the junction-to-ambient thermal resistance (theta_JA) is approximately 28 °C/W on a 4-layer board, which yields a 4.6 °C rise above ambient — well within margin. Still, stitch the central exposed pad with 9 thermal vias to a continuous ground pour, per the RGC PCB layout guideline, so the analog ground is low-impedance for ADC readings.
Route the 16 monitor inputs as guarded, length-matched traces with at least 8 mil width on a 4-layer board. Place 100 nF RC filters at each MONx pin within 2 mm to suppress switching-converter noise from corrupting the 12-bit ADC. Keep digital PMBus/SDAS/SCL traces separated by at least a 4 mil gap from the analog monitor nets. Avoid running monitor nets parallel to switching phase nodes for more than 5 mm.
Do not populate the UCD90910 (12-rail) or UCD90124 (8-rail) firmware on a UCD90160 board even though they share the package: the unused MONx pins must be tied off and the GP input/output map is different. Reverse engineering them as drop-ins will trip the firmware CRC check on first power-up. For volume runs of designs that may downscale, populate the correct family member from the start and treat pin compatibility as a PCN-controlled choice.
Compliance Information
RoHS compliant per TI product page. Not AEC-Q100 qualified — the UCD90160ARGCT is targeted at industrial, telecom, and server environments rather than automotive. Fusion Digital Power Designer GUI is the configuration tool.
