ADC/DAC
Produtos (2518)
LTC2180IUP - 16-Bit 25Msps Dual ADC | Analog Devices
The Analog Devices LTC2180IUP is a 16-bit, 25Msps low-power dual simultaneous-sampling analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm, exposed pad) package. It provides two fully differential input channels with pipelined architecture, 77 dB SNR, and 90 dB spurious-free dynamic range, optimized for demanding communications, instrumentation, and high-speed signal-acquisition designs. Background Knowledge: An ADC (Analog-to-Digital Converter) is a semiconductor device that converts continuous analog signals into discrete digital codes. Dual ADCs contain two independent converter channels that sample simultaneously, which is essential when the relative phase between two signals carries information (for example, I/Q baseband signals in a radio receiver, or paired sensor channels in sonar and vibration analysis). The LTC2180 family sits within the broader hierarchy: ADC -> data converter -> signal chain IC -> mixed-signal semiconductor. Key features include 25 Msps sampling per channel, simultaneous sampling of both inputs, ultralow jitter of 0.07 ps RMS that enables IF undersampling, an internal common-mode reference buffer, and a flexible CMOS/LVDS digital output bus. The pipelined architecture delivers low latency while maintaining 16-bit resolution at full throughput. Total power dissipation is approximately 250 mW per channel at full rate. Typical applications include diversity receivers and I/Q digitizers in software-defined radio, multi-channel ultrasound front ends, precision data acquisition, wideband spectrum analyzers, and medical imaging subsystems. The wide input bandwidth and excellent SFDR make it suitable for direct-IF sampling. Design consideration: because both channels share a common clock and reference, layout must keep analog and digital grounds separated under the exposed pad. Aggressive LC filtering on the analog AVDD supply is critical to maintain SNR at high input frequencies. This page synthesizes distributor pricing, drop-in same-package alternatives from the same LTC family, and practical design notes not consolidated in the manufacturer datasheet, providing decision-ready information for engineers selecting a 16-bit dual ADC for a multi-channel signal chain.
LTC2181IUP - 16-Bit 40Msps Dual ADC, DDR LVDS | Analog Devices
The Analog Devices LTC2181IUP is a 16-bit, 40 Msps, dual-channel simultaneous-sampling pipelined analog-to-digital converter (ADC) with DDR LVDS outputs, housed in a 64-pin QFN (9x9 mm) package. It features two ADC channels sampling at the same instant, 77 dBFS signal-to-noise ratio (SNR) at 5 MHz input, and 90 dBFS spurious-free dynamic range (SFDR), all from a single 1.8 V analog supply and an optional LVDS swing supply. The device is specified over the industrial temperature range of -40C to +85C. An ADC (Analog-to-Digital Converter) is a data converter that samples continuous analog voltage signals and produces discrete digital codes. Within the broader semiconductor hierarchy, the LTC2181IUP belongs to the high-speed ADC family, which is itself a sub-category of data converters, sitting alongside DACs (Digital-to-Analog Converters) and CODECs. High-speed pipeline ADCs like the LTC2181 are the workhorse of communications, test and measurement, and defense signal chains where wide analog bandwidth and high dynamic range are required. Key features include integrated bypass capacitance to reduce PCB complexity, selectable input ranges of 1 Vp-p to 2 Vp-p, an internal duty-cycle stabilizer that corrects for clock duty-cycle distortion, and a low-jitter clock receiver that accepts CMOS, LVDS, or sine-wave inputs. Each channel is independently controlled via a 3-wire SPI-compatible serial interface, allowing per-channel gain, offset, and phase calibration without external trim. The 64-lead QFN package with an exposed pad provides a thermal resistance (theta_JC) suitable for the device's low 100 mW per channel power dissipation. The LTC2181's pipelined architecture is built around 16 internal stages with error correction, and its DDR LVDS digital interface transmits two data bits per clock cycle, halving the number of required output traces and easing PCB routing. The combination of low jitter (< 70 fs), high SNR, and selectable LVDS swing (350 mV or 700 mV) makes it well suited for driving FPGAs and ASICs over short board-to-board links. Typical applications include cellular base-station receive paths, multiband, multimode digital receivers, antenna array processing, communications test equipment, and high-end imaging systems such as medical ultrasound and non-destructive flaw detection. The dual simultaneous-sampling architecture is particularly important for I/Q demodulation and for any system that requires phase-coherent acquisition of two signals. When designing with the LTC2181IUP, place the 1.8 V analog decoupling capacitors within 5 mm of the AVDD pins and bond the exposed pad to a clean ground plane to keep digital switching currents out of the analog return path. The DDR LVDS output timing is referenced to the rising clock edge; be sure to use the same source-matched impedance (100 ohm differential) on all data and clock pairs to avoid inter-symbol jitter. This page synthesizes distributor pricing, drop-in same-family alternatives (LTC2180, LTC2182), and practical layout guidance that is not contained in the bare manufacturer datasheet.
LTC2182CUP - 16-Bit 65Msps Dual ADC, 77dB SNR | Analog Devices
The Analog Devices LTC2182CUP is a 16-bit, 65 Msps low-power dual simultaneous-sampling analog-to-digital converter (ADC) housed in a 64-pin QFN (UP) 9x9 mm package. It delivers 77 dB SNR and 90 dB spurious-free dynamic range (SFDR) with ultralow 0.07 ps RMS jitter, enabling undersampling of high-IF signals with excellent linearity. The dual-channel pipelined architecture drives a total IC power dissipation under 230 mW at 65 Msps, making it suitable for thermally-constrained multi-channel systems. An ADC (analog-to-digital converter) is a data-converter IC that samples continuous analog signals and produces quantized digital codes, and the pipelined sub-class achieves high sampling rates by cascading multiple low-resolution stages. Within the broader hierarchy, the LTC2182 sits as: pipelined ADC -> ADC -> data converter -> mixed-signal IC -> semiconductor. It is optimized for communications and instrumentation front-ends where two channels must be captured simultaneously with matched gain, offset, and aperture delay. Key features include a 1.7 V to 1.9 V analog supply (1.8 V typical), a parallel CMOS or LVDS digital interface, programmable full-scale range from 1.0 V to 2.0 V peak-to-peak, and an optional external reference. Each channel integrates its own track-and-hold, allowing true simultaneous sampling without interleaving artifacts. Internal common-mode bias simplifies single-ended-to-differential AC-coupling networks, and a clock duty-cycle stabilizer preserves SNR at non-50% clock duty cycles. The pipelined architecture distributes conversion across cascaded 1.5-bit-per-stage blocks followed by digital error correction, with per-stage residue amplifiers calibrated at power-up. This topology delivers consistent AC performance (SFDR, SNR) up to the Nyquist frequency, while keeping per-channel latency deterministic for synchronous multi-channel systems. Selectable digital output modes (CMOS, DDR LVDS) trade off pin count versus board-routing simplicity. Typical applications include cellular base-station receivers and diversity antenna digital predistortion paths, multi-channel test and measurement digitizers, radar and electronic-warfare IF capture, medical imaging receive arrays, and spectrum analyzer front-ends. The 0.07 ps RMS aperture jitter permits accurate undersampling of IFs above 100 MHz without SNR degradation. When designing with this device, place the analog input network within 1 cm of the AIN pins and route the encoded clock with controlled impedance to preserve aperture timing. Power-supply decoupling requires a 10 uF bulk plus 0.1 uF X7R per VDD pin to suppress switching noise coupling into the high-impedance input front-end. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the standalone manufacturer datasheet.
LTC2182IUP - 16-Bit 65Msps Dual ADC | Analog Devices
The Analog Devices LTC2182IUP is a 16-bit, 65 Msps, low-power, dual-channel simultaneous-sampling analog-to-digital converter (ADC) housed in a 64-pin QFN (9 mm x 9 mm) exposed-pad package. It features two matched pipeline ADC cores, on-chip DDR LVDS or CMOS outputs, and AC performance that delivers 77 dB SNR and 90 dB spurious-free dynamic range (SFDR), making it well suited for digitizing high-frequency, wide-dynamic-range signals in communications, instrumentation, and defense systems. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous-time analog waveform and converts it into a discrete digital code word. In the broader IC taxonomy, dual pipeline ADCs sit between general-purpose successive-approximation-register (SAR) ADCs and high-speed flash converters; the pipeline architecture enables sample rates from tens to hundreds of Msps while maintaining 14-16 bit resolution. The LTC2182IUP belongs to the family of dual ADC ICs that simultaneously sample two channels - critical for I/Q signal processing, diversity receivers, and beamforming where channel-to-channel phase matching must be preserved. Key features of the LTC2182IUP include a programmable LVDS/CMOS output mode, internal clock duty-cycle stabilizer, digital randomizer and dither, and pin-selectable full-scale input range between 1 Vp-p and 2 Vp-p. The integrated common-mode bias and on-chip reference simplify board design, while the selectable low-power and low-noise operating modes let designers trade idle current against dynamic range at the application level. Internally, each channel uses a 16-stage switched-capacitor pipeline fronted by a wide-bandwidth differential sample-and-hold amplifier. The digital back-end includes a 16-bit flash error-correction block plus configurable output serializers that can drive either CMOS or DDR LVDS, easing interfacing with FPGAs and dedicated ASICs. Typical applications for the LTC2182IUP include direct-IF sampling diversity receivers, multi-antenna software-defined-radio (SDR) front ends, vector signal analyzers, time-interleaved digital oscilloscopes, and medical imaging receivers. Communications system designers value the 90 dB SFDR for clean decoding of multi-carrier waveforms such as LTE, 5G NR, and DVB-S2X. A primary design consideration is LVDS-versus-CMOS output trade-off: LVDS provides up to 65 Msps with robust noise immunity across backplanes, while single-wire CMOS output halves the I/O count at the expense of speed when lower sample rates suffice. Always tie the exposed pad (EP) directly to a low-impedance ground plane - the EP is the primary thermal and ground return for both ADC channels. This page synthesizes distributor pricing, drop-in package-matched alternatives, and practical layout notes that extend beyond the manufacturer datasheet.
LTC2183CUP - 16-Bit 80Msps Dual ADC Low Power QFN-64 | Analog Devices
The Analog Devices LTC2183CUP is a 16-bit, 80Msps dual-channel simultaneous-sampling low-power analog-to-digital converter (ADC) housed in a 64-lead QFN (UP) 9x9 mm package with exposed pad. The device delivers 76.8 dB SNR and 90 dB SFDR with ultra-low 0.07 psRMS aperture jitter, making it well suited for digitizing wide-dynamic-range, high-frequency signals. A dual pipelined ADC is a converter architecture that uses multiple low-resolution stages in series, with each stage sampling and converting a portion of the input before passing residue to the next stage; digital error correction aligns the bits. Dual ADCs are commonly used in diversity receivers, I/Q demodulation, and medical imaging where two correlated channels must be digitized on the same clock edge. The LTC2183 family belongs to the broader converter IC category, sitting between analog front-end signal conditioning and downstream DSP/FPGA logic. Key features include user-selectable LVDS / DDR LVDS / CMOS output modes, a parallel low-voltage CMOS port option, an SPI port for configuration, internal dither to improve small-signal linearity, and a clock duty-cycle stabilizer. Total power consumption is approximately 390 mW at 80 Msps, far below competing dual ADCs. Input range is 2 Vp-p (fully differential) with an internal PGA. Typical applications include communications receivers, basestation diversity channels, I/Q demodulators, portable instrumentation, medical imaging front-ends, and non-destructive ultrasonic testing. The exposed-pad QFN-64 package enables low thermal resistance for sustained operation. When designing in the LTC2183CUP, pay close attention to differential input network design, layout of the clock tree, and decoupling strategy on both AVDD and DVDD rails to realize the full 76.8 dB SNR specification.
LTC2184IUP - 16-Bit 105Msps Dual ADC, 64-QFN | Analog Devices
The Analog Devices LTC2184IUP is a 16-bit, 105 Msps dual-channel simultaneous-sampling pipelined analog-to-digital converter housed in a 64-pin QFN (9x9) package. It features two differential or single-ended analog inputs, an integrated high-performance reference, and on-chip CMOS or LVDS digital outputs, making it suitable for communications, medical imaging, and instrumentation front ends. A pipelined ADC (also called a pipeline converter) is a type of analog-to-digital converter that resolves an input sample through a cascade of low-resolution stages, each producing one or more output bits. Pipelined ADCs offer a balanced trade-off between speed, resolution, and power: they sample at tens to hundreds of Msps while maintaining 12- to 16-bit resolution, making them the dominant architecture in communications infrastructure, radar, and IF-sampling applications. Within the broader power-management and signal-chain hierarchy, a high-speed ADC like the LTC2184 sits downstream of an analog front-end (amplifier, anti-alias filter) and upstream of an FPGA or ASIC that performs digital signal processing. The LTC2184 delivers 76.8 dB SNR and 90 dB spurious-free dynamic range (SFDR), with ultralow 0.07 ps RMS aperture jitter that allows accurate undersampling of IF frequencies. According to the Analog Devices datasheet, this dual ADC supports CMOS, LVDS, or DDR LVDS digital output modes to ease interfacing with FPGAs and ASICs, and offers a low-power shutdown mode for power-sensitive designs. Typical applications include cellular base-station receivers, software-defined radio, MRI gradient amplifiers, radar signal conditioning, and high-speed data acquisition cards. The wide input bandwidth also makes it appropriate for cable infrastructure and spectrum analyzer designs. When laying out the PCB, treat each analog input as a 50 ohm or 100 ohm differential transmission line and use a solid ground plane beneath the 64-QFN exposed pad to minimize coupling and to keep the device within its thermal envelope. Always drive the encode clock with a low-jitter source; any clock jitter directly adds to the aperture uncertainty and degrades SNR. This page synthesizes distributor pricing, drop-in same-family alternatives (LTC2185IUP, LTC2183IUP), and practical layout guidance that is not consolidated in the manufacturer datasheet PDF alone.
LTC2188CUP - 16-Bit 20Msps Dual ADC | Analog Devices
The Analog Devices LTC2188CUP is a two-channel simultaneous-sampling 16-bit analog-to-digital converter designed for digitizing high-frequency, wide-dynamic-range signals, and is offered in a 64-pin QFN (UP) package. It samples at up to 20 Msps per channel with a pipelined architecture, delivering 77 dB SNR and 90 dB spurious-free dynamic range (SFDR) for communications, instrumentation, and medical imaging front-ends. The converter integrates low-jitter clock conditioning, CMOS or DDR LVDS digital output modes, and configurable full-scale input ranges. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog signals into discrete digital codes at a sample rate determined by an external clock. Pipelined ADCs like the LTC2188CUP use multiple low-resolution stages to digitize one input sample per clock cycle after an initial pipeline latency, achieving a balance of high sample rate, moderate resolution, and low power consumption. They sit within the broader hierarchy of signal chain components: ADC -> data converter -> mixed-signal IC -> semiconductor, and are typically paired with low-noise front-end amplifiers, anti-alias filters, and FPGA or ASIC capture logic. Key features of the LTC2188CUP include dual simultaneous 20 Msps channels, 16-bit resolution, 77 dB SNR at 10 MHz input, 90 dB SFDR, support for CMOS and DDR LVDS output interfaces, an internal sample-and-hold, and programmable analog input span. Integrated digital features such as data-ready outputs and pattern generation simplify board bring-up and FPGA/ASIC handshake design. The part is offered in commercial (C) and industrial/extended temperature grades. The LTC2188CUP uses a multi-stage pipelined core with proprietary dithering techniques that linearize the transfer function and improve small-signal SFDR. A differential input architecture rejects common-mode noise and even-order harmonics, while on-chip bias generation reduces the external component count. The device consumes roughly 65 mW per channel at 20 Msps and includes power-down modes for portable or multi-channel systems where thermal budget is constrained. Typical applications include digital oscilloscopes and wideband data acquisition, communications receivers and software-defined radio (SDR) front-ends, medical ultrasound beamformers, and industrial imaging systems. The dual-channel simultaneous sampling makes the LTC2188CUP particularly well-suited to I/Q baseband digitizers and multi-antenna diversity receivers where channel-to-channel timing alignment is critical. When designing with the LTC2188CUP, pay close attention to the analog input network: a wideband, differential, low-distortion front-end (such as the ADA4932 or LTC6406) is typically required to preserve the converter's 90 dB SFDR. Decouple the AVDD and DVDD rails with separate low-ESR ceramic capacitors placed as close as possible to the package pins, and route differential pairs with controlled 100-ohm impedance on the PCB. This page synthesizes verified distributor pricing, drop-in alternatives drawn from the LTC2188 family (LTC2185, LTC2186, LTC2187) plus pin-compatible ADI 16-bit ADCs, and practical design notes not found in the manufacturer datasheet alone.
LTC2188IUP - 16-Bit 20Msps Dual ADC | Analog Devices
The Analog Devices LTC2188IUP is a 16-bit, 20 Msps, dual-channel simultaneous-sampling pipelined analog-to-digital converter housed in a 64-lead QFN (9 x 9 mm) package with exposed pad. Each channel delivers 77 dB SNR and 90 dB spurious-free dynamic range, making the part well-suited for digitizing high-frequency, wide-dynamic-range signals in demanding communications and instrumentation systems. The IUP suffix denotes the industrial-grade -40C to +85C operating range required for telecom baseband, multi-standard radio and direct-IF conversion paths. What is a dual simultaneous-sampling ADC? A dual simultaneous-sampling ADC is a category of data converter that captures two analog input channels through independent sample-and-hold circuits driven by a common clock, ensuring channel-to-channel skew of picoseconds rather than nanoseconds. In the broader taxonomy, the LTC2188 family sits within successive-approximation / pipelined ADCs -> data converters -> mixed-signal ICs -> signal chain components. The simultaneous-sample property matters whenever phase or IQ information must be preserved between channels (communications, beamforming, predistortion). Key features of the LTC2188IUP include a single 1.8 V analog supply, LVDS or CMOS configurable digital outputs, optional internal dither to improve SFDR at small input levels, and a low-jitter clock input that relaxes the noise requirements of the front-end PLL. The device integrates input kick-back suppression and selectable input bandwidth, allowing direct connection to wideband IF signals without a front-end buffer. Power dissipation scales gracefully with sample rate, allowing the user to throttle clocks for low-power idle states. Typical applications for the LTC2188IUP span LTE/4G/5G baseband digitizers, multi-standard software-defined radios, multi-channel data acquisition front-ends for instrumentation and beamforming arrays used in radar and medical imaging prototypes. Designers who must interface to an FPGA typically use the LVDS output mode to preserve timing margins at 20 Msps on long board traces. When laying out a board for the LTC2188IUP, keep analog and digital ground returns joined only at the exposed pad, and place the 0.1 microfarad ceramic decoupling capacitors within 1 mm of each supply pin. The 64-QFN exposed pad must be soldered to a continuous ground plane to keep junction temperature within the 31 C/W theta_JA budget; inadequate thermal connection will degrade AC linearity.
LTC2190CUKG - 16-Bit, 25Msps Dual ADC | Analog Devices
The Analog Devices LTC2190CUKG is a 16-bit, 25 Msps, dual-channel, simultaneous-sampling pipelined analog-to-digital converter (ADC) housed in a 52-pin QFN (7x8 mm) package with an exposed pad. Key parameters include 77 dB SNR and 90 dB spurious-free dynamic range (SFDR), ultralow 0.07 ps RMS jitter for undersampling of IF frequencies, and low power dissipation that simplifies thermal design in multichannel systems. An ADC (Analog-to-Digital Converter) is a semiconductor device that converts continuous-time analog signals into discrete digital codes. Within the data-converter taxonomy, the LTC2190 sits in the high-speed pipelined-ADC category, which itself is a subcategory of data converters, signal chain ICs, and mixed-signal semiconductors. Pipelined ADCs use multiple low-resolution stages to achieve high sampling rates while keeping per-stage power modest, and dual-channel parts such as this enable I/Q baseband capture or two-antenna diversity receivers from a single device. The two analog channels sample simultaneously, preserving phase information between channels - essential for diversity reception, MIMO front-ends, and quadrature demodulation. Digital outputs are serial LVDS with optional internal termination and adjustable output levels to maintain clean signal integrity across backplanes or long PCB traces. A typical front-end configuration places the LTC2190 downstream of a transformer-coupled differential driver and a band-pass anti-alias filter. Architecturally the converter uses a high-bandwidth track-and-hold front end and a multi-stage pipelined core calibrated at the factory, with on-chip reference and an internal common-mode buffer. The 0.07 ps RMS aperture jitter lets designers undersample IF signals well above the Nyquist rate without SNR penalty, and the 77 dB SNR sustains >12 effective bits at full input bandwidth. Differential input range is programmable around the 1.5 V common-mode point, simplifying interface to popular RF downconverters. Primary applications include cellular base-station receiver digitizers, multi-carrier software-defined radio front-ends, medical ultrasound beamformer ADCs, and multi-axis industrial vibration / instrumentation digitizers. Choosing this device versus a generic 16-bit ADC trades generic low cost for guaranteed dual-channel simultaneity, calibrated dynamic range, and direct compatibility with serial LVDS FPGA interfaces. Design considerations: route the analog and digital grounds as separate planes joined only under the exposed pad, place the input RC network within 5 mm of the inputs, and supply the LVDS section from a clean low-noise LDO such as an LT3042 or LT3045 to achieve the published 90 dB SFDR. The exposed pad must be soldered for thermal continuity and low inductance ground. This page synthesizes distributor pricing, drop-in same-package alternatives (LTC2192CUKG, LTC2191CUKG, LTC2185CUKG, LTC2174CUKG-14) drawn from the LTC2190/91/92 family datasheet, and practical layout notes not found in the manufacturer datasheet alone.
LTC2190IUKG - 16-Bit 25Msps Dual ADC | Analog Devices
The Analog Devices LTC2190IUKG is a 2-channel simultaneous-sampling 16-bit pipelined analog-to-digital converter (ADC) that operates at 25 Msps per channel, housed in a 52-pin QFN (7x8) package. It achieves 77 dB SNR and 90 dB spurious-free dynamic range (SFDR) at the full sampling rate, with low power consumption suitable for portable and densely-packed multi-channel systems. The converter accepts differential inputs and is designed for digitizing high-frequency, wide-dynamic-range signals. A pipelined ADC is a multi-stage converter architecture that performs a coarse quantization in early stages and a fine resolution in later stages, enabling high sampling rates with moderate latency. Pipelined ADCs sit within the broader hierarchy of analog-to-digital converter architectures: they occupy the middle ground between successive-approximation (SAR) ADCs, which offer low power but lower speeds, and flash ADCs, which offer the highest speeds at much lower resolution and far higher power. The pipelined architecture makes the LTC2190 ideal for communications receivers, IF digitization, and multi-channel data-acquisition systems where 16-bit resolution and 25 Msps speed must coexist with low power. The LTC2190IUKG features 2 fully differential input channels, each with its own sample-and-hold, allowing simultaneous capture of two analog signals. An internal high-precision bandgap reference and reference buffer simplify external component count, while a flexible LVDS/CMOS-compatible data output interface and SPI-compatible serial programming port allow per-channel gain and offset calibration, output format selection, and power-down modes. Industrial temperature grade (-40C to +85C) operation is supported, with optional extended-grade variants for harsher environments. In typical communications and instrumentation designs, the LTC2190IUKG is used in the IF signal path of multi-carrier wireless base stations, in medical ultrasound beamformers, in radar and LiDAR front-ends, and in high-channel-count portable oscilloscopes and spectrum analyzers. The 52-QFN (7x8 mm) package provides a compact footprint with an exposed thermal pad, enabling PCB designs that stack two ADCs on a single board while keeping the thermal path within safe limits. When designing with the LTC2190IUKG, the most important considerations are differential input drive (a balun or ADC driver is normally required), PCB layout of the analog and digital grounds, and proper decoupling of the internal reference and supply pins. Following Analog Devices' reference-layout guidance in the datasheet typical-application section is strongly recommended to achieve the published 77 dB SNR. This page synthesizes distributor pricing, drop-in alternatives (LTC2180CUP, LTC2184IUP, LTC2156IUP-14, and others), and practical design notes not assembled in any single source - including same-package comparison data and cross-brand reference points that help engineers evaluate board-level alternatives.
LTC2191CUKG - 16-Bit 40Msps Dual ADC | Analog Devices
The Analog Devices LTC2191CUKG is a 16-bit, 40 Msps, dual-channel simultaneous-sampling pipelined analog-to-digital converter (ADC) housed in a 52-pin QFN (7x8 mm) package. The device features two simultaneously sampled input channels, 77 dB SNR, 90 dB spurious-free dynamic range (SFDR), and 0.07 psRMS ultra-low aperture jitter, allowing accurate undersampling of high-IF frequency signals. It operates from a single 1.8 V supply and is specified over the commercial 0C to 70C range. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog waveforms into discrete digital codes for processing by DSPs, microcontrollers, or FPGAs. Within the converter family, the pipelined architecture (sub-type of high-speed ADC) uses multiple cascaded low-resolution stages to achieve 14-16 bit precision at tens to hundreds of Msps, making it the standard choice for digitizing wideband communications signals, software-defined radio, and medical imaging front-ends. The LTC2191CUKG belongs to the broader category of data converters -> ADCs -> high-speed ADCs -> pipelined ADCs. Key features include 73.4 dBFS signal-to-noise ratio at 9.7 MHz input, two independently timed differential input channels, an internal bypassable bandgap reference, and low power dissipation that simplifies thermal design in multi-channel systems. CMOS and LVDS output modes allow flexible digital interconnect with FPGAs and ASICs. The LTC2191CUKG employs a multi-stage pipelined architecture with proprietary digital calibration that corrects capacitor mismatch and comparator offset in the background, yielding 16-bit linearity without external trimming. The exposed pad on the bottom of the QFN package must be soldered to a grounded copper pour to achieve the rated AC performance and provide thermal dissipation. Typical applications include cellular base-station receivers, IF digitization in software-defined radio, portable test and measurement instrumentation, medical imaging front-ends (ultrasound beamformers), and multi-antenna MIMO systems where two channels of matched phase performance are required. When designing with this device, allocate sufficient PCB area for the exposed-pad thermal via array and keep analog input traces impedance-matched (typically 100 ohm differential) and length-matched between the two channels. Decouple AVDD and DVDD with 10uF plus 0.1uF ceramic capacitors placed within 5 mm of the supply balls to preserve SNR and SFDR at full sampling rate. This page synthesizes distributor pricing, same-family dual-ADC drop-in alternatives, and practical PCB layout guidance not consolidated in the manufacturer datasheet.
LTC2191IUKG - 16-Bit, 40Msps Dual ADC | Analog Devices
The Analog Devices LTC2191IUKG is a 16-bit, 40 Msps, low-power, dual-channel simultaneous-sampling pipelined analog-to-digital converter housed in a 52-lead QFN (7x8 mm) package. It pairs two 16-bit ADC cores that sample on the same clock edge, delivering 40 Msps per channel (80 Msps aggregate) with 77 dB SNR and 90 dB spurious-free dynamic range (SFDR) for demanding wide-bandwidth communications, radar, and instrumentation front ends. What is a dual ADC? A dual ADC integrates two matched analog-to-digital converter channels on a single die, sharing a common reference and clock distribution. This eliminates channel-to-channel skew in multi-antenna or I/Q signal chains, which is critical for diversity receivers, MIMO transceivers, and beamforming arrays where phase and amplitude matching between channels defines system-level SNR. Key differentiating specifications include 16-bit resolution at 40 Msps per channel, 77 dB SNR, 90 dB SFDR, an integrated DDR LVDS serial digital interface (1-, 2-, or 4-bit-per-sample modes) to minimize board traces, and optional internal LVDS termination with adjustable output levels. Per-channel power dissipation is approximately 40 mW per ADC at 40 Msps, and a low-power sleep mode drops consumption below 1 mW for portable or battery-backed applications. Architecturally, the LTC2191IUKG uses a multi-stage switched-capacitor pipeline frontend paired with an on-chip bandgap reference and proprietary digital error correction. The device accepts differential or single-ended inputs and supports bipolar input ranges through the common-mode voltage on each channel, simplifying front-end driver amplifier design. Its DDR LVDS outputs and selectable data-rate modes (one-bit, two-bit, or four-bit per sample) significantly reduce parallel bus width and ease FPGA capture. Typical applications include diversity antenna receivers, multiband, multimode cellular base stations, phased-array radar digitizers, test and measurement equipment, medical imaging, and high-speed instrumentation. Two synchronized channels make the LTC2191IUKG particularly well suited to I/Q direct-conversion receivers where IQ amplitude and phase matching directly determine image rejection. A key design consideration is preserving the input common-mode voltage with a wideband ADC driver such as the LT1994 or ADA4937; AC coupling at the input must include a DC bias network to keep common-mode within the ADC's input range. LVDS trace length matching is also critical to maintain setup/hold margins at the FPGA. This page synthesizes distributor pricing, drop-in alternatives within the Linear Technology / Analog Devices pipelined-ADC family, and practical layout guidance beyond what is summarized in the manufacturer datasheet.
LTC2192IUKG - 16-bit 65Msps Dual ADC | Analog Devices
The Analog Devices (formerly Linear Technology) LTC2192IUKG is a 16-bit, 65 Msps, dual-channel, simultaneous-sampling pipelined analog-to-digital converter (ADC) housed in a 52-pin QFN (7x8 mm) package with an exposed pad. The two on-chip ADCs are clocked from a single clock input and share a common reference, providing matched-channel dynamic performance for I/Q demodulation and diversity receivers. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous-time continuous-amplitude analog signals into discrete digital codes. Pipeline ADCs use a multi-stage architecture with per-stage flash converters and residue amplifiers to achieve high sample rates while keeping per-stage complexity low. Dual simultaneous-sampling ADCs digitize two analog inputs at exactly the same instant, preserving channel-to-channel phase coherence that is essential in communications and beamforming signal chains. The LTC2192 family sits within the broader ADC hierarchy: ADC -> data converter -> signal chain IC -> mixed-signal semiconductor. Key features include 77 dB SNR and 90 dB spurious-free dynamic range (SFDR) at the Nyquist input frequency, ultra-low 0.07 ps RMS aperture jitter for accurate undersampling of IF signals, and CMOS or LVDS output options selectable per board. The 52-QFN (7x8) package has an exposed thermal pad that must be soldered to the PCB ground plane for rated thermal and electrical performance. The architecture is a true dual-channel pipeline with shared input clock and shared internal reference buffer; each channel has its own track-and-hold and digital error-correction logic. The 0.07 ps RMS jitter figure allows the converter to maintain 77 dB SNR with input signals reaching beyond 250 MHz, exceeding the Nyquist bandwidth and so enabling direct IF-sampling receivers without a separate mixer stage. Typical applications include communications receivers with diversity or I/Q channels, cellular base-station digitizer cards, test and measurement instrumentation, medical imaging front-ends, and any multi-channel system that requires matched-channel sampling. Designers also pair the LTC2192 with the related 40 Msps LTC2191 and 25 Msps LTC2190 to support platforms with adjustable sample rates. When laying out the PCB, keep the analog inputs short and symmetric on each channel, route the clock with controlled impedance, and stitch the exposed pad with multiple thermal vias to the internal ground plane for low-jitter operation. Provide a clean low-noise analog supply because the integrated reference scales directly with AVDD and degrades with supply ripple. Decouple AVDD and DVDD with 1 µF and 0.1 µF ceramic capacitors placed within 5 mm of each supply pin. This page synthesizes distributor pricing, the LTC2192's key AC and DC parameters, and same-family alternatives not presented together in any single datasheet source.
LTC2193IUKG - 16-Bit 80Msps Dual ADC, 76.8dB SNR | ADI
The Analog Devices LTC2193IUKG is a 16-bit, 80Msps, dual-channel, simultaneously-sampling low-power analog-to-digital converter (ADC) in a 52-pin QFN (7x8 mm) package. It features 76.8 dB SNR and 90 dB SFDR, total power dissipation of 249 mW (125 mW per channel), 0.07 psRMS ultra-low jitter, and serial LVDS outputs (1, 2, or 4 bits per channel). What is a high-speed dual ADC? A dual ADC is a single integrated circuit that contains two independent, simultaneously-sampling analog-to-digital converters sharing a common clock and reference. The 'simultaneous sampling' property preserves the phase relationship between the two analog inputs, which is critical in diversity receivers, MIMO wireless links, and I/Q demodulation paths. The 16-bit resolution provides 96 dB of dynamic range, placing dual ADCs in the signal chain hierarchy between front-end amplifiers/anti-alias filters and the digital baseband FPGA or ASIC. Key features of the LTC2193IUKG include a single 1.8V analog supply, single 1.8V to 3.3V output supply, CMOS or DDR LVDS output modes, and pin-compatible scalability within the LTC2195/LTC2194/LTC2193 family (125/105/80 Msps). The pipelined architecture integrates a high-bandwidth differential sample-and-hold with on-chip voltage reference, while the data clock output simplifies FPGA capture. Its ultralow aperture jitter of 0.07 psRMS enables accurate undersampling of high-IF signals. The LTC2193IUKG utilizes a 16-stage pipelined architecture with digital error correction. The wide input bandwidth supports IF sampling well above 100 MHz, and the configurable LVDS lane count (1-, 2-, or 4-bit-per-channel) allows designers to trade pin count for board complexity. The 'I' suffix denotes the industrial temperature grade of -40C to +85C, suitable for non-automotive commercial and industrial environments. Typical applications include communications receivers, cellular base stations, smart antenna systems, handheld radio links, ultrasound and medical imaging, and portable instrumentation. In each of these, the simultaneous sampling and low power-to-performance ratio directly translate to reduced PCB area, longer battery life, or denser channel count. When designing with this device, pay close attention to PCB layout: the analog and digital grounds should be separated and joined only at the exposed pad, and the input traces must be length-matched differential pairs to preserve SNR. Use the LTC217x/LTC219x family evaluation kit as a reference for the analog input network, clock distribution, and LVDS routing. This page synthesizes distributor pricing, drop-in compatible alternatives from the same datasheet family, and practical PCB design notes not present on standard distributor listings, providing an engineer-focused decision brief for selecting the LTC2193IUKG.
LTC2194CUKG - 16-Bit 105Msps Dual ADC, 52-QFN | Analog Devices
The Analog Devices LTC2194CUKG is a 16-bit, 105 Msps, dual-channel simultaneous-sampling pipelined analog-to-digital converter (ADC) housed in a 52-pin QFN (7x8 mm) package. It is part of the LTC2195/LTC2194/LTC2193 family, delivering 76.8 dB SNR and 90 dB spurious-free dynamic range (SFDR) at full Nyquist input, with ultralow 0.07 psRMS aperture jitter that enables undersampling of IF frequencies in communications systems. Two fully differential analog inputs support per-channel conversion at up to 105 Msps with independent CMOS output ports, making the part well-suited for diversity receivers, MIMO front-ends, and multi-antenna baseband digitizers. A pipelined ADC is a high-speed data converter architecture that uses multiple low-resolution flash stages interleaved with sample-and-hold and DAC residue amplifiers to achieve conversion rates from tens to hundreds of megasamples per second, while preserving 12-16 bit resolution. Pipelined ADCs occupy the middle ground between successive-approximation (SAR) converters (low power, single-shot) and flash ADCs (very high speed, low resolution). Within a signal chain they sit between the analog front end (LNA, mixer, anti-alias filter) and the digital back end (FPGA, ASIC, DSP), translating conditioned IF or baseband signals into parallel LVDS/LVCMOS words for downstream demodulation or beamforming. The dual-channel, simultaneous-sampling variant, which the LTC2194CUKG represents, is a key building block in modern multi-channel radio designs. Key features of the LTC2194CUKG include a 1.8 V analog and digital supply rail, an optional low-power mode that reduces consumption at lower sample rates, programmable full-scale input range, and per-channel LVCMOS outputs that interface directly with FPGAs. The 52-QFN exposed-pad package provides a low thermal-resistance path and a compact 7x8 mm PCB footprint, enabling dense multi-channel layouts. Typical applications include LTE and W-CDMA diversity receivers, multi-carrier base-station digitizers, cable-headend downstream capture, medical imaging receivers, and radar/EW intermediate-frequency sampling. The ultralow jitter also makes it suitable for direct IF sampling in software-defined radio and instrumentation front ends. When designing with the LTC2194CUKG, use a low-jitter clock source (such as a clean crystal oscillator or clock distribution IC) and tightly bypass each supply pin with a 0.1 microfarad ceramic capacitor plus a bulk tantalum or polymer cap. The exposed thermal pad must be soldered to a continuous ground plane for thermal and electrical performance, and the analog and digital ground planes should be joined only at the IC's exposed pad to prevent digital switching noise coupling into the analog inputs. This page synthesizes the official datasheet, current distributor pricing, drop-in same-family and cross-brand alternatives, and practical design notes not found on standard distributor product pages.
LTC2194IUKG - 16-Bit 105Msps Dual ADC | Analog Devices
The Analog Devices LTC2194IUKG is a 2-channel, simultaneous-sampling 16-bit analog-to-digital converter (ADC) operating at 105 Msps, designed for digitizing high-frequency, wide-dynamic-range signals. It is housed in a 52-pin QFN (7x8 mm) package and supports a 1.7 V to 1.9 V analog supply with LVDS digital outputs, delivering 76.8 dB SNR and 90 dB spurious-free dynamic range (SFDR) at the rated sample rate. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog voltage signals into discrete digital codes. The category hierarchy is: ADC -> data converter -> signal chain IC -> mixed-signal semiconductor. Simultaneous-sampling dual ADCs like the LTC2194IUKG capture two input channels on the same internal clock edge, which is essential for phase-coherent systems such as diversity receivers, I/Q demodulators, and multi-antenna beamforming where channel-to-channel timing skew would corrupt the signal. Key performance features include 0.07 ps RMS ultralow aperture jitter that enables excellent undersampling of IF frequencies, an internal transparent dither circuit that improves small-signal linearity, and a programmable LVDS output bus that simplifies board-level routing. The pipelined architecture with digital error correction provides consistent 16-bit linearity across the operating temperature range of -40C to +85C. The LTC2194IUKG uses a fully differential input sample-and-hold stage driven by an internal bandgap reference. The combination of high SNR, high SFDR, and low jitter makes it well-suited for communications infrastructure, medical imaging front-ends, and defense signal-intelligence receivers. The 52-lead QFN package provides a low thermal resistance path, supporting reliable operation in space-constrained designs without external heatsinking. Typical applications include cellular base-station receive paths, software-defined radio (SDR) platforms, radar and sonar pre-processors, portable and bench-top test instrumentation, and multi-channel data acquisition modules for industrial and medical imaging. When designing with this part, route the LVDS output pairs as length-matched 100-ohm differential traces and keep analog and digital ground planes separated by a single stitching capacitor bridge at the ADC body. Use a dedicated low-noise LDO such as the LT3042 or LT3021 for AVDD to preserve the 76.8 dB SNR. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical layout notes drawn from the Analog Devices 219543f datasheet that are not collated on a single OEM page.
LTC2195CUKG - 16-Bit 125Msps Dual ADC | Analog Devices
The Analog Devices LTC2195CUKG is a 2-channel, simultaneous-sampling 16-bit pipelined analog-to-digital converter (ADC) capable of 125 Msps per channel, housed in a 52-pin QFN (7x8 mm) package. It delivers 76.8 dB SNR and 90 dB spurious-free dynamic range (SFDR) with ultra-low 0.07 ps RMS aperture jitter, allowing accurate undersampling of high-IF signals. The device operates from a single 1.7 V to 1.9 V analog supply with a separate 1.7 V to 1.9 V digital supply, providing flexible power-domain isolation for mixed-signal boards. A pipelined ADC is a high-speed successive-approximation architecture in which the input sample passes through multiple low-resolution flash stages, each stage producing one or more output bits and a residual that is amplified into the next stage. By correcting digital errors across stages, pipelined ADCs reach 12-16 bit resolution at sample rates from 50 Msps to over 500 Msps, making them the workhorse for communications, radar, and instrumentation front-ends. The LTC2195 belongs to the broader class of low-power dual ADCs, which sit in the signal chain between analog conditioning (amplifiers, filters) and the FPGA or DSP that performs demodulation, FFT, or beamforming. Key features include differential inputs with 650 MHz full-power bandwidth, LVDS digital outputs, a serial SPI port for configuration, and a typical power dissipation near 250 mW per channel at 125 Msps. Built-in digital gain and offset correction, dither, and a programmable output demultiplexer reduce downstream FPGA logic and simplify PCB routing. The 52-QFN exposed-pad package keeps thermal resistance low for reliable operation across the -40 C to +85 C commercial range. Typical applications include multi-carrier 3G/4G LTE base-station receivers, diversity radio and MIMO front-ends, IF-sampling software-defined radio (SDR), high-speed oscilloscopes and digitizers, medical imaging ultrasound, and radar/EW digitizing channels. The simultaneous-sampling dual-channel architecture is especially valuable where two channels must be captured with deterministic inter-channel skew, such as I/Q demodulation or phased-array beamforming. When designing with the LTC2195CUKG, the analog input network should be a bandwidth-limited differential transformer or fully-differential driver; the LVDS output traces must be length-matched to within 50 mil, and the exposed pad must be soldered to a continuous ground plane. Good decoupling of both AVDD and DVDD rails with 10 uF bulk and 0.1 uF ceramic capacitors is critical for meeting the 76.8 dB SNR spec. This page synthesizes Analog Devices datasheet parameters, distributor pricing as of 2026-10-13, drop-in same-package alternatives, and practical design guidance not found on the manufacturer product page alone.
LTC2195IUKG - 16-Bit 125Msps Dual ADC | Analog Devices
The Analog Devices LTC2195IUKG is a dual-channel, 16-bit, 125 Msps low-power analog-to-digital converter (ADC) housed in a 52-pin QFN (7x8 mm) package with exposed pad. The device targets demanding communications applications, delivering 76.8 dB SNR and 90 dB spurious-free dynamic range (SFDR) while consuming only 535 mW total power. It supports parallel, SPI/serial, and LVDS digital interfaces for flexible FPGA or ASIC downstream connectivity. What is a pipelined ADC? A pipelined analog-to-digital converter is a multi-stage architecture that converts an analog input into a digital code by passing the signal through a cascade of low-resolution flash sub-converter stages. Each stage resolves a portion of the input, holds the residue, and hands it to the next stage. Pipelined ADCs are favored for sample rates between about 10 Msps and several hundred Msps because they balance high throughput, moderate latency, and excellent dynamic performance at moderate power. The LTC2195IUKG sits inside the broader taxonomy of ADC -> data converter -> signal chain IC -> semiconductor. Key features include simultaneous sampling of two independent analog inputs, ultralow 0.07 ps RMS aperture jitter enabling IF undersampling, and a single +1.8V supply rail that simplifies power-tree design. The pipelined core is paired with a high-bandwidth input buffer and integrated reference, eliminating the need for an external ADC driver in many applications. 1ku list pricing begins at $165.77 as of 2026-10-13. The LTC2195 is part of a pin-compatible family that also includes the 105 Msps LTC2194 and 80 Msps LTC2193, plus speed-grade variants within each speed node. This pin compatibility allows designers to swap parts on the same PCB to trade speed for power without re-laying out the board, which is particularly useful in multi-channel receiver platforms. Typical applications include multi-carrier software-defined radio (SDR) receivers, LTE and 3G base-station digitizers, portable test and measurement instrumentation, medical imaging front-ends, and dual-antenna diversity receivers. The dual simultaneous sampling makes the device especially suited to I/Q demodulation, diversity reception, and any system requiring phase-coherent two-channel capture. When designing in the LTC2195IUKG, ensure the analog inputs are AC-coupled with a bias network biased at the common-mode voltage to preserve linearity. The exposed pad must be soldered to a sufficient ground copper pour to keep junction temperature within the -40C to +85C industrial range at full 125 Msps throughput. This page synthesizes distributor pricing, pin-compatible same-family variants, and practical design notes that complement, but are not contained in, the official Analog Devices datasheet.
LTC2201IUK - 16-Bit 20Msps ADC, 48-QFN | Analog Devices
The Analog Devices LTC2201IUK is a 20 Msps, 16-bit pipelined analog-to-digital converter (ADC) designed for digitizing high-frequency, wide-dynamic-range signals with input frequencies up to 380 MHz, housed in a 48-pin QFN (7x7 mm) package. The device features a programmable-gain-amplifier (PGA) front end, on-chip dither for low-amplitude linearity, and AC performance of 81.6 dB SNR with 100 dB spurious-free dynamic range (SFDR). An ADC (analog-to-digital converter) is a data-converter integrated circuit that samples continuous analog signals and outputs discrete digital codes; pipelined ADCs such as the LTC2201IUK are the dominant architecture for 10-250 Msps converters in communications, test and measurement, and radar/imaging front ends. Within the broader converter hierarchy, this part belongs to the high-speed, high-resolution (>= 16-bit, >= 10 Msps) sub-category that sits between precision SAR converters and ultra-fast flash converters. Its 16-bit resolution places it in the precision-instrumentation tier where DC accuracy, low noise, and wide spurious-free dynamic range are critical. Key features include 81.6 dB SNR and 100 dB SFDR at 5 MHz input, 250 MHz full-power input bandwidth, 2.25 Vp-p or 1.5 Vp-p selectable input range, internal dither for SFDR improvement, and a low-jitter clock-to-data output interface. The pipelined architecture enables high throughput while maintaining low power consumption; a separate output supply supports LVDS or CMOS digital interfaces. Industrial temperature range (-40C to +85C) is supported in this IUK variant. Typical applications include cellular base-station receivers, radar and electronic-warfare systems, digital oscilloscopes, spectrum analyzers, and medical imaging front ends. The wide 250 MHz analog input bandwidth and 20 Msps throughput make the LTC2201IUK well suited to IF-sampling architectures where the ADC samples a down-converted IF directly without an additional mixer stage. The high SFDR of 100 dB is critical for spectral purity in cellular and radar receivers. When designing with this part, drive the analog input with a low-noise, low-distortion differential amplifier (such as the AD8352 or ADL5562) and place the anti-alias filter as close to the inputs as possible. Decouple the analog and digital supplies separately to prevent switching noise from coupling back into the analog front end; the exposed pad on the QFN-48 must be soldered to the ground plane for both electrical and thermal reasons. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet. All specifications are reproduced from the LTC2201 datasheet retrieved 2026-10-13.
LTC2202CUK - 16-Bit 10Msps ADC, 48-QFN | Analog Devices
The Analog Devices LTC2202CUK is a 16-bit, 10Msps pipelined analog-to-digital converter (ADC) optimized for digitizing high-frequency, wide-dynamic-range signals up to 380MHz input bandwidth. It is housed in a 48-lead QFN (7x7 mm) package and is the commercial-temperature (0C to +70C) member of the LTC2202/2203 ADC family from Linear Technology (now part of Analog Devices). According to the Analog Devices LTC2202 product page, key AC performance figures include 81.6dB SNR and 100dB spurious-free dynamic range (SFDR), with the front-end PGA allowing the input range to be optimized between approximately 1V and 2.25V p-p for best linearity. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed Nyquist ADC architecture that processes the analog input through a series of low-resolution flash stages, each stage producing a digital residue that is digitized by the next stage. Pipelined ADCs offer a strong trade-off between sampling rate (single-digit MHz to several hundred MHz), resolution (8-16 bits), and power consumption, making them the dominant choice for communications infrastructure, instrumentation, and defense signal acquisition. The LTC2202CUK sits in the 16-bit, 10-25Msps segment commonly used in IF digitizers, ultrasound receivers, and spectrum analyzers. Key features of the LTC2202CUK include 10Msps guaranteed sampling rate, 81.6dB SNR and 100dB SFDR at the Nyquist input, integrated PGA front end for input scaling, LVDS or CMOS-compatible digital outputs, optional dither for improved low-level linearity, and an internal reference. The part operates from a single 3.3V analog supply plus a 3.3V or optional 2.5V digital supply, simplifying system power design. The 48-QFN (7x7) package offers a low thermal-resistance path for the commercial-grade temperature range. The LTC2202CUK is typically used in cellular base-station digitizers, satellite receivers, medical imaging front-ends, sonar processing, and high-speed instrumentation. Its 380MHz input bandwidth makes it suitable for undersampling IF signals, while the integrated PGA helps reject out-of-band noise before the sampling capacitor. Designers should note that the LTC2203 (25Msps) shares the same pinout, which allows a single PCB layout to serve both sampling-rate variants. This page synthesizes distributor pricing, drop-in same-package alternatives, application recommendations, and datasheet references that are not found together on a single distributor listing.
LTC2203CUK - 16-Bit, 25Msps ADC, 48-QFN | Analog Devices
The Analog Devices LTC2203CUK is a 16-bit, 25 Msps pipelined analog-to-digital converter housed in a 48-pin QFN (7x7 mm) package. It delivers 81.6 dB SNR and 100 dB spurious-free dynamic range (SFDR), making it suitable for digitizing high-frequency, wide-dynamic-range signals with input frequencies up to 380 MHz. The integrated PGA front end allows the input range to be optimized for the application, and DC linearity is specified at ±4 LSB INL and ±1 LSB DNL with no missing codes. A pipelined ADC is a high-speed Nyquist-rate data converter that resolves an analog input by cascading low-resolution stages and applying digital correction. Pipelined ADCs dominate communications, instrumentation, and imaging front-ends where tens-of-MHz sampling and 12-16 bit resolution must coexist. As a member of this family, the LTC2203CUK targets demanding AC and DC use cases that previously required separate high-speed and precision converters. Key features of the LTC2203CUK include 81.6 dB SNR at 25 Msps, 100 dB SFDR with input tones near Nyquist, ±4 LSB INL and ±1 LSB DNL maximum, and an input bandwidth exceeding 380 MHz. Differential clock and input architecture minimize even-order distortion, while internal bias resistors simplify reference decoupling. The 48-QFN (7x7) package provides a compact footprint with an exposed pad for thermal performance. The LTC2203CUK is built on a BiCMOS process combining bipolar input buffers with CMOS pipeline stages and CMOS output drivers. The BiCMOS input stage preserves low distortion at high IF frequencies, while CMOS logic keeps power consumption and digital noise manageable. Internal reference and CMFB networks simplify board-level design and reduce BOM count. Typical applications include cellular basestation receiver IF digitizers, medical ultrasound beamforming front-ends, high-end instrumentation, software-defined radio, and CCD/camera imaging pipelines. The combination of wide analog input bandwidth and clean dynamic range allows the converter to be placed directly after a low-IF mixer or transimpedance amplifier with minimal analog gain staging. When designing with this device, pay attention to input common-mode voltage, differential clock duty cycle, and reference decoupling. The output data is LVDS-compatible in the related LTC2203 family; the LTC2203CUK exposes CMOS outputs that require careful trace impedance and length matching to avoid degrading SFDR at full sampling rate. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
LTC2204CUK - 16-Bit 40MSPS ADC, 48-QFN | Linear Technology/ADI
The Linear Technology (Analog Devices) LTC2204CUK is a 16-bit, 40MSPS pipelined analog-to-digital converter housed in a 48-pin QFN (7x7 mm) package with exposed pad. It pairs the LTC2205 (65MSPS) family in a lower-speed variant, offering the same wideband dynamic range performance (79dB SNR, 100dB SFDR) and an ultralow 90fsRMS jitter front end, enabling undersampling of IF signals up to 700 MHz. The on-chip PGA front end allows the input range to be optimized for the application. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous analog voltage signals into discrete digital codes. Pipelined ADCs in the LTC2204 family are designed for high-frequency, wide-dynamic-range signal acquisition, sitting in the broader hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. They are widely used in communications, instrumentation, and defense applications where both sampling rate and spurious-free dynamic range are critical. Key features include 79dB SNR and 100dB SFDR for demanding communications links, 90fsRMS aperture jitter for excellent noise performance when undersampling high-IF signals, an integrated PGA to optimize input range, and ±4LSB INL / ±1LSB DNL (no missing codes). The differential input architecture and on-chip reference simplify board design while the LVDS/CMOS-compatible output interface supports direct connection to FPGAs and DSPs. The architecture is a 16-stage pipelined switched-capacitor ADC with proprietary linear technology that achieves excellent AC linearity. The 90fsRMS jitter and -88dBFS noise floor at 70MHz input (typical) make it suitable for direct IF sampling in software-defined radios and broadband receivers. Internal references and a digital output randomizer reduce idle tones. Typical applications include cellular base-station receivers, software-defined radio, instrumentation and test equipment, broadband communications, and radar/IF signal processing. The wide input bandwidth also supports medical imaging front ends and spectrum analyzer digitizers. When designing with the LTC2204CUK, ensure the analog input network is properly terminated to 50 ohms with a wideband transformer or differential driver; the exposed pad must be soldered to a low-impedance ground plane for thermal relief and noise performance. Use the internal reference for prototyping and an external reference when temperature stability is critical. This page synthesizes distributor pricing, verified same-brand LTC2204 family drop-in alternatives, and practical design notes not consolidated in any single datasheet - giving engineers a single source for selection, replacement, and BOM risk analysis.
LTC2204IUK - 16-Bit 40Msps ADC | Analog Devices
The Analog Devices LTC2204IUK is a 16-bit, 40 Msps pipelined analog-to-digital converter (ADC) housed in a 48-pin QFN (7x7 mm) package, designed for digitizing high-frequency, wide-dynamic-range signals up to 700 MHz input frequency. The IUK suffix indicates the industrial temperature grade (-40C to +85C), and the device ships in a 48-lead exposed-pad QFN that supports the part's 1.1 W typical power dissipation. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes at a programmable sampling rate. The 16-bit pipelined architecture sits between successive-approximation register (SAR) ADCs (lower speed, lower power) and flash ADCs (highest speed, lowest resolution), making pipelined 16-bit converters the workhorse choice for communications, radar, and instrumentation applications where both wide analog bandwidth and >80 dB dynamic range are required. The LTC2204IUK belongs to the broader category of mixed-signal ICs > data converters > high-speed ADCs. Key features include 79 dB SNR, 100 dB spurious-free dynamic range (SFDR), and ultralow 90 fs RMS aperture jitter, which together permit accurate undersampling of IF signals in software-defined radio and digital oscilloscope front ends. The maximum DC specifications reach +/-4 LSB INL and +/-1 LSB DNL with no missing codes, ensuring monotonic transfer curves for precision measurement. A programmable PGA front end (0 dB to 36 dB in 4 dB steps) lets the user optimize the input range from 1.0 Vp-p to 2.5 Vp-p, easing interface to a wide variety of IF amplifiers and SAW filters. Architecturally, the LTC2204IUK uses a multi-stage switched-capacitor pipeline with digital error correction, followed by an internal reference and LVDS/CMOS-compatible output drivers. Optional LVDS outputs (one or two lanes) reduce digital switching noise in noise-sensitive systems, while the CMOS mode provides simpler interfacing to FPGAs and ASICs without external LVDS receivers. Typical applications include cellular base-station receivers, digital oscilloscopes, spectrum analyzers, satellite modems, and medical imaging. The 700 MHz input bandwidth with 90 fs jitter makes it well suited for undersampling intermediate frequencies in IF-sampling radio designs. A design consideration: the exposed thermal pad (pin 49) must be soldered to a continuous ground plane to achieve the rated 1.1 W dissipation. Thevenin termination on each LVDS output pair is recommended when driving long PCB traces or backplane connectors to preserve signal integrity. This page synthesizes distributor pricing, drop-in alternatives, application notes, and design notes that are not present on the manufacturer datasheet, giving engineers a single source for sourcing, comparing, and designing with the LTC2204IUK.
LTC2205CUK - 16-Bit 65Msps ADC, 79dB SNR | Analog Devices
The Analog Devices LTC2205CUK is a 16-bit, 65 Msps pipelined analog-to-digital converter housed in a 48-pin QFN (7x7 mm) package with exposed pad. It is designed for digitizing high-frequency, wide dynamic range signals up to 700 MHz input frequency, delivering 79 dB SNR and 100 dB spurious-free dynamic range (SFDR). The internal PGA front end allows the input range to be optimized between 1.5 Vp-p and 2.25 Vp-p, giving system designers flexibility between SNR and SFDR trade-offs. The -65 lA / -40 lA versions are identical except for sample rate. A pipelined ADC is a successive-stage converter architecture that achieves high sample rates with multi-bit per stage error correction. The LTC2205 uses this approach to combine 16-bit resolution at 65 Msps while maintaining low latency suitable for many communications and instrumentation channels. AC performance is the headline figure for this class of converter, where SNR, SFDR, and aperture jitter determine achievable dynamic range. Key features include ultralow aperture jitter of 90 fsRMS, enabling excellent noise performance for IF/RF undersampling architectures; ±4 LSB INL and ±1 LSB DNL maximum with no missing codes; CMOS-compatible digital outputs with optional LVDS operation; an integrated PGA with 1.5 Vp-p to 2.25 Vp-p input range; and shutdown / nap modes for power-sensitive applications. The 48-lead QFN (7x7) package with exposed pad provides thermal resistance suited to the commercial temperature grade. Architecturally, the LTC2205 uses 9 pipeline stages with proprietary digital error correction. The analog input is fully differential for best harmonic performance, and the on-chip sample-and-hold can accurately capture signals at the full 65 Msps rate. An internal bandgap reference sets full-scale. The data interface can be configured as single-ended CMOS or low-voltage differential- LVDS for noise-immune board-level routing. This combination suits the LTC2205 to demanding communications, radar, and test-instrumentation front ends where small-signal capture at high IF frequencies is required. Typical applications include cellular base-station digitizers where the part's 700 MHz input bandwidth permits direct IF sampling, cable head-end CMTS / upstream receivers, radar and EW intermediate-frequency sampling, broadband satellite receivers, and high-end instrumentation digitizers such as digital oscilloscopes and spectrum analyzers. The differential input structure rejects common-mode noise from the upstream driver amplifier. When designing with this part, drive the analog input with a low-noise, low-distortion differential op-amp or balun network, keep analog and digital ground returns separated under the exposed pad, and bypass the supply pins with low-ESR ceramics placed within a few millimeters of the device. The PGA setting directly trades SNR against SFDR and should be chosen after measuring both against the system target. This page synthesizes distributor pricing, parametric drop-in alternatives, and practical front-end design notes not found in the manufacturer datasheet.