LTC2182IUP - 16-Bit 65Msps Dual ADC | Analog Devices
N.º da peça: LTC2182IUP ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $132.45 | $132,45 |
| 10 | $119.2 | $1.192,00 |
| 100 | $110.85 | $11.085,00 |
| 500 | $107.5 | $53.750,00 |
| 1.000 | $105.93 | $105.930,00 |
LTC2182IUP Visão geral
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous-time analog waveform and converts it into a discrete digital code word. In the broader IC taxonomy, dual pipeline ADCs sit between general-purpose successive-approximation-register (SAR) ADCs and high-speed flash converters; the pipeline architecture enables sample rates from tens to hundreds of Msps while maintaining 14-16 bit resolution. The LTC2182IUP belongs to the family of dual ADC ICs that simultaneously sample two channels - critical for I/Q signal processing, diversity receivers, and beamforming where channel-to-channel phase matching must be preserved.
Key features of the LTC2182IUP include a programmable LVDS/CMOS output mode, internal clock duty-cycle stabilizer, digital randomizer and dither, and pin-selectable full-scale input range between 1 Vp-p and 2 Vp-p. The integrated common-mode bias and on-chip reference simplify board design, while the selectable low-power and low-noise operating modes let designers trade idle current against dynamic range at the application level.
Internally, each channel uses a 16-stage switched-capacitor pipeline fronted by a wide-bandwidth differential sample-and-hold amplifier. The digital back-end includes a 16-bit flash error-correction block plus configurable output serializers that can drive either CMOS or DDR LVDS, easing interfacing with FPGAs and dedicated ASICs.
Typical applications for the LTC2182IUP include direct-IF sampling diversity receivers, multi-antenna software-defined-radio (SDR) front ends, vector signal analyzers, time-interleaved digital oscilloscopes, and medical imaging receivers. Communications system designers value the 90 dB SFDR for clean decoding of multi-carrier waveforms such as LTE, 5G NR, and DVB-S2X.
A primary design consideration is LVDS-versus-CMOS output trade-off: LVDS provides up to 65 Msps with robust noise immunity across backplanes, while single-wire CMOS output halves the I/O count at the expense of speed when lower sample rates suffice. Always tie the exposed pad (EP) directly to a low-impedance ground plane - the EP is the primary thermal and ground return for both ADC channels.
This page synthesizes distributor pricing, drop-in package-matched alternatives, and practical layout notes that extend beyond the manufacturer datasheet.
Alternativas drop-in para LTC2182IUP — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com LTC2182IUP (mesmo formato e footprint) — diferindo em Package, Resolution, RoHS Status, Number of Channels, SNR.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
LTC2181IUP
✅ Drop-In✓ Em estoque
$25.2 / unidade
Ver ficha técnica →LTC2180IUP
✅ Drop-In✓ Em estoque
$48 / unidade
Ver ficha técnica →LTC2156IUP-14
✅ Drop-In✓ Em estoque
$134.1 / unidade
Ver ficha técnica →LTC2182IUP Classificações máximas e características elétricas
| Resolução | 16 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate | 65 Msps |
| Architecture | Pipelined |
| Input Channels | 2 differential |
| SNR | 77 dB |
| SFDR | 90 dB |
| Data Output Interface | Parallel CMOS / DDR LVDS / SPI configurable |
| Input Range | 1 Vp-p to 2 Vp-p (programmable) |
| Encapsulamento | 64-QFN EP (9x9 mm) |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant (#PBF suffix) |
| 1ku List Price (reference) | $105.93 (as of 2026-10-13) |
Configuração de pinos do LTC2182IUP
| Pino 1 | GND — Ground |
| Pino 2 | VAIN1+ — Channel 1 positive analog input |
| Pino 3 | VAIN1- — Channel 1 negative analog input |
| Pino 4 | GND — Ground |
| Pino 5 | GND — Ground |
| Pino 6 | ENC+ — Encode clock positive input |
| Pino 7 | ENC- — Encode clock negative input |
| Pino 8 | GND — Ground |
| Pino 9 | VREF — Reference voltage pin |
| Pino 10 | SENSE — Reference mode select |
| Pino 11 | GND — Ground |
| Pino 12 | VDD — Analog supply |
| Pino 13 | OGND — Output driver ground |
| Pino 14 | OVDD — Output driver supply |
| Pino 15 | D15 — Data bit 15 (MSB) |
| Pino 16 | D14 — Data bit 14 |
| Pino 17 | D13 — Data bit 13 |
| Pino 18 | D12 — Data bit 12 |
| Pino 19 | D11 — Data bit 11 |
| Pino 20 | D10 — Data bit 10 |
| Pino 21 | D9 — Data bit 9 |
| Pino 22 | D8 — Data bit 8 |
| Pino 23 | D7 — Data bit 7 |
| Pino 24 | D6 — Data bit 6 |
| Pino 25 | D5 — Data bit 5 |
| Pino 26 | D4 — Data bit 4 |
| Pino 27 | D3 — Data bit 3 |
| Pino 28 | D2 — Data bit 2 |
| Pino 29 | D1 — Data bit 1 |
| Pino 30 | D0 — Data bit 0 (LSB) |
| Pino 31 | NC — Not connected (per datasheet) |
| Pino 32 | DRCLK — Data-ready clock output |
| Pino 33 | OVDD — Output driver supply |
| Pino 34 | OGND — Output driver ground |
| Pino 35 | CLKOUT- — Clock output negative |
| Pino 36 | CLKOUT+ — Clock output positive |
| Pino 37 | OGND — Output driver ground |
| Pino 38 | OVDD — Output driver supply |
| Pino 39 | CSEL — CMOS / LVDS clock select |
| Pino 40 | MODE — Output mode select |
| Pino 41 | GND — Ground |
| Pino 42 | VAIN2+ — Channel 2 positive analog input |
| Pino 43 | VAIN2- — Channel 2 negative analog input |
| Pino 44 | GND — Ground |
| Pino 45 | OF — Output flag overflow indicator |
| Pino 46 | OR — Output flag out of range |
| Pino 47 | GND — Ground |
| Pino 48 | SDOUT — SPI serial data output |
| Pino 49 | SDIO — SPI serial data input/output |
| Pino 50 | SCK — SPI clock input |
| Pino 51 | CS — SPI chip select |
| Pino 52 | GND — Ground |
| Pino 53 | D2THR — D2 threshold logic input |
| Pino 54 | NC — Not connected (per datasheet) |
| Pino 55 | VDD — Analog supply |
| Pino 56 | GND — Ground |
| Pino 57 | VAIN2+ — Channel 2 positive analog input (mirror) |
| Pino 58 | VAIN2- — Channel 2 negative analog input (mirror) |
| Pino 59 | GND — Ground |
| Pino 60 | VAIN1+ — Channel 1 positive analog input (mirror) |
| Pino 61 | VAIN1- — Channel 1 negative analog input (mirror) |
| Pino 62 | GND — Ground |
| Pino 63 | VDD — Analog supply |
| Pino 64 | EP — Exposed pad - ground and thermal pad |
Aplicações típicas
LTC2182IUP é adequado para 7 aplicaçãos: Diversity Communications Receiver, Software-Defined Radio Front End, Medical Ultrasound Imaging Receiver, Vector Signal Analyzer Capture, High-Speed Digital Oscilloscope, Industrial Test and Measurement, Radar Pulse Receiver Front-End.
Diversity Communications Receiver
The LTC2182IUP's two matched simultaneous-sampling 16-bit ADC cores digitize I and Q baseband streams from dual antennas with sub-sample phase alignment, eliminating the channel mismatch that plagues interleaved designs. Its 90 dB SFDR preserves multi-carrier EVM margin in 4G LTE and 5G NR receivers where spurious tones can otherwise lift the noise floor and force a diversity combining loss of 1-3 dB.
Recomendado
Software-Defined Radio Front End
Direct-IF sampling SDR platforms use the LTC2182IUP to digitize intermediate-frequency signals without an analog downconversion stage, simplifying RF plumbing and enabling multi-standard operation. The 65 Msps per channel sample rate covers up to 32 MHz of usable Nyquist bandwidth, while the LVDS output mode cleanly fans out to an FPGA fabric where digital downconversion runs in firmware rather than analog mixers.
Recomendado
Medical Ultrasound Imaging Receiver
Beamforming ultrasound receivers sum dozens of analog front-end channels, so each ADC's sample-to-sample latency must be deterministic across temperature. The LTC2182IUP's matched-channel pipeline latency and 77 dB SNR enable RF-to-baseband pulse echo conversion at 10-40 Msps with enough dynamic range to resolve small cysts alongside large reflectors. CMOS output mode here keeps FPGA pin count manageable when stacking 16 or 32 channels.
Recomendado
Vector Signal Analyzer Capture
Vector signal analyzers need high SFDR to characterize transmitter mask compliance of Wi-Fi 6/6E and 5G NR signals. The LTC2182IUP's 90 dB SFDR comfortably exceeds the 80 dB floor needed to spot third-order intermodulation spurs in 1024-QAM constellations without false-pass results. The 65 Msps speed digitizes 20 MHz LTE or 40 MHz Wi-Fi channels with margin.
Recomendado
High-Speed Digital Oscilloscope
Time-interleaved oscilloscopes pair identical ADCs across parallel channels; using the LTC2182IUP's matched dual cores eliminates the gain and offset skew that single-channel parts can introduce. The 16-bit resolution, while not at the leading edge for scopes (14 bits is typical), suits communications probing and protocol analyzer cards where signal integrity matters more than ENOB.
Recomendado
Industrial Test and Measurement
ATE (automatic test equipment) and precision instrumentation digitize multi-channel strain-gauge, accelerometer, or thermocouple arrays where channel-to-channel phase coherence matters more than extreme speed. The LTC2182IUP's dual-core matched architecture simplifies synchronous sampling for vibration and modal analysis test rigs, while the 77 dB SNR ensures dynamic range sufficient for harmonic analysis.
Recomendado
Radar Pulse Receiver Front-End
Phased-array radar receivers require matched simultaneous sampling across dozens of antenna channels with deterministic latency; the LTC2182IUP provides one dual-channel block per radar tile, and its programmable 1 Vp-p / 2 Vp-p input range accommodates both low-IF and high-IF downconverted outputs. The 90 dB SFDR keeps spur-induced false targets below the radar's minimum detectable signal threshold.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para LTC2182IUP — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | LTC2181IUP | LTC2180IUP | LTC2156IUP-14 |
|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN EP (9x9 mm) | 64-QFN EP (9x9 mm) - same | 64-QFN EP (9x9 mm) - same | 64-QFN EP (9x9 mm) - same |
| Resolution | 16 bit | 16 bit - same | 16 bit - same | 14 bit |
| Sample Rate | 65 Msps | 40 Msps | 25 Msps | 40 Msps |
| Number of Channels | 2 (simultaneous sampling) | 2 (simultaneous sampling) - same | 2 (simultaneous sampling) - same | 2 (simultaneous sampling) - same |
| Output Interface | CMOS / DDR LVDS / SPI | CMOS / DDR LVDS / SPI - same | CMOS / DDR LVDS / SPI - same | CMOS / DDR LVDS / SPI |
| 1ku Reference Price | $105.93 | Lower (40 Msps) | Lower (25 Msps) | Lower |
Principais diferenciais
- Highest sample rate in the LTC2182 dual-ADC family (vs LTC2181IUP)
- Dual-channel simultaneous sampling eliminates phase mismatch (vs TI ADS6425 (single-channel 16-bit 65 Msps ADC))
- Industry-leading 90 dB SFDR at 65 Msps (vs Generic 16-bit 65 Msps ADC competitors)
- Programmable CMOS / DDR LVDS output mode (vs TI ADS6425 (CMOS-only output))
Notas de projeto
The 64-QFN EP exposed pad is the primary ground and thermal return for both ADC channels. Stitch the EP to a low-impedance ground plane with at least 9 thermal vias (1.0 mm pitch, 0.3 mm diameter) directly under the package, and avoid routing any signal trace across the EP region. Analog and digital ground planes must be separated and tied together at a single point under or beside the EP to avoid return-current coupling that would degrade SNR.
Estimate (input values: 65 Msps, LVDS output mode, 1.8 V supplies): decouple each VDD pin with a 1 uF X7R 0402 ceramic placed within 3 mm of the pin plus a 100 nF X7R 0402 in parallel for high-frequency noise. Keep analog VDD and OVDD rails isolated through separate ferrite beads fed from a common low-noise LDO. Add a pi-filter (LC network) on each supply rail entering the ADC footprint to attenuate board-level switching noise from upstream DC-DC converters.
Drive the encode clock (ENC+/ENC-) from a low-jitter clock generator with RMS jitter well below 300 fs; phase noise translates directly to ADC SNR degradation. For LVDS output mode at 65 Msps, keep trace lengths matched within 5 mm across the 16-bit data bus, terminate at the FPGA receiver with 100 ohm differential pairs, and use a series resistor of 22-33 ohm at the ADC side to damp reflections.
Do not leave the SENSE pin floating: tie it to VREF for internal 2.5 V reference mode, or to ground for an external reference. Driving the analog inputs above the absolute maximum (typically 3.6 V with supply on) can latch the input ESD structure and cause long-term degradation; add input clamps if signal source is hot-pluggable. The CSEL and MODE pins must be static during reset - toggling them mid-sample causes data corruption.
Route differential analog input traces (VAIN1+ / VAIN1- and VAIN2+ / VAIN2-) symmetrically with constant 50 ohm differential impedance, and bring them in from the same edge of the BGA-style pinout to avoid crossing. Place the input anti-alias filter RC network within 5 mm of the analog input pins; the typical filter is 25 ohm resistor with 10 pF differential NPO capacitor for the 65 Msps Nyquist band.
Informações de conformidade
RoHS compliance confirmed by #PBF suffix on the part number per Analog Devices part-number convention. The base LTC2182IUP (without #PBF) is non-RoHS; for new designs always specify #PBF. AEC-Q100 automotive qualification not obtained per the datasheet identification; for automotive-grade reception consider the AD9268 automotive variant or other qualified dual ADCs.
