LTC2195IUKG - 16-Bit 125Msps Dual ADC | Analog Devices
N.º da peça: LTC2195IUKG ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $165.77 | $165,77 |
| 10 | $152.5 | $1.525,00 |
| 100 | $138.2 | $13.820,00 |
| 500 | $128 | $64.000,00 |
| 1.000 | $165.77 | $165.770,00 |
LTC2195IUKG Visão geral
What is a pipelined ADC? A pipelined analog-to-digital converter is a multi-stage architecture that converts an analog input into a digital code by passing the signal through a cascade of low-resolution flash sub-converter stages. Each stage resolves a portion of the input, holds the residue, and hands it to the next stage. Pipelined ADCs are favored for sample rates between about 10 Msps and several hundred Msps because they balance high throughput, moderate latency, and excellent dynamic performance at moderate power. The LTC2195IUKG sits inside the broader taxonomy of ADC -> data converter -> signal chain IC -> semiconductor.
Key features include simultaneous sampling of two independent analog inputs, ultralow 0.07 ps RMS aperture jitter enabling IF undersampling, and a single +1.8V supply rail that simplifies power-tree design. The pipelined core is paired with a high-bandwidth input buffer and integrated reference, eliminating the need for an external ADC driver in many applications. 1ku list pricing begins at $165.77 as of 2026-10-13.
The LTC2195 is part of a pin-compatible family that also includes the 105 Msps LTC2194 and 80 Msps LTC2193, plus speed-grade variants within each speed node. This pin compatibility allows designers to swap parts on the same PCB to trade speed for power without re-laying out the board, which is particularly useful in multi-channel receiver platforms.
Typical applications include multi-carrier software-defined radio (SDR) receivers, LTE and 3G base-station digitizers, portable test and measurement instrumentation, medical imaging front-ends, and dual-antenna diversity receivers. The dual simultaneous sampling makes the device especially suited to I/Q demodulation, diversity reception, and any system requiring phase-coherent two-channel capture.
When designing in the LTC2195IUKG, ensure the analog inputs are AC-coupled with a bias network biased at the common-mode voltage to preserve linearity. The exposed pad must be soldered to a sufficient ground copper pour to keep junction temperature within the -40C to +85C industrial range at full 125 Msps throughput.
This page synthesizes distributor pricing, pin-compatible same-family variants, and practical design notes that complement, but are not contained in, the official Analog Devices datasheet.
Alternativas drop-in para LTC2195IUKG — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com LTC2195IUKG (mesmo formato e footprint) — diferindo em Package, Operating Temperature Range, Sample Rate, Input Type, Resolution.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
LTC2195CUKG
✅ Drop-In✓ Em estoque
$110.85 / unidade
Ver ficha técnica →LTC2194IUKG
✅ Drop-In✓ Em estoque
$92.8 / unidade
Ver ficha técnica →LTC2193IUKG
✅ Drop-In✓ Em estoque
$78 / unidade
Ver ficha técnica →LTC2191IUKG
✅ Drop-In✓ Em estoque
$62.95 / unidade
Ver ficha técnica →LTC2190IUKG
✅ Drop-In✓ Em estoque
$18.21 / unidade
Ver ficha técnica →LTC2195IUKG Classificações máximas e características elétricas
| Resolução | 16 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate | 125 Msps |
| Architecture | Pipelined |
| Input Type | Single-ended and differential |
| SNR | 76.8 dB |
| SFDR | 90 dB |
| Aperture Jitter | 0.07 ps RMS |
| Power Dissipation | 535 mW |
| Digital Interface | Parallel / SPI (serial) / LVDS |
| Encapsulamento | 52-pin QFN (7x8 mm) with exposed pad |
| Tipo de montagem | Surface Mount |
| Faixa de temperatura de operação | -40C to +85C (Industrial) |
| 1ku List Price | $165.77 (starting, as of 2026-10-13) |
| Temperature Grade | Industrial |
| Lead-Free / RoHS | Yes (PBF suffix indicates lead-free per-tray) |
Configuração de pinos do LTC2195IUKG
| Pino 1 | GND — Ground (per datasheet package pinout) |
| Pino 2 | AINA+ — Channel A positive analog input |
| Pino 3 | AINA- — Channel A negative analog input |
| Pino 4 | GND — Ground |
| Pino 5 | AINB+ — Channel B positive analog input |
| Pino 6 | AINB- — Channel B negative analog input |
| Pino 7 | GND — Ground |
| Pino 8 | VCM — Common-mode voltage output |
| Pino 9 | VREF — Reference voltage bypass |
| Pino 10 | SENSE — Reference mode select (per datasheet) |
| Pino 11 | GND — Ground |
| Pino 12 | OGND — Output driver ground |
| Pino 13 | D0A — Channel A data bit 0 (or LVDS pair in LVDS mode) |
| Pino 14 | D1A — Channel A data bit 1 |
| Pino 15 | D2A — Channel A data bit 2 |
| Pino 16 | D3A — Channel A data bit 3 |
| Pino 17 | D4A — Channel A data bit 4 |
| Pino 18 | D5A — Channel A data bit 5 |
| Pino 19 | D6A — Channel A data bit 6 |
| Pino 20 | D7A — Channel A data bit 7 |
| Pino 21 | D8A — Channel A data bit 8 |
| Pino 22 | D9A — Channel A data bit 9 |
| Pino 23 | D10A — Channel A data bit 10 |
| Pino 24 | D11A — Channel A data bit 11 |
| Pino 25 | D12A — Channel A data bit 12 |
| Pino 26 | D13A — Channel A data bit 13 |
| Pino 27 | D14A — Channel A data bit 14 |
| Pino 28 | D15A — Channel A data bit 15 |
| Pino 29 | OF_A — Channel A data overflow flag |
| Pino 30 | CLKOUT_A — Channel A clock output / DCO |
| Pino 31 | OGND — Output driver ground |
| Pino 32 | D0B — Channel B data bit 0 |
| Pino 33 | D1B — Channel B data bit 1 |
| Pino 34 | D2B — Channel B data bit 2 |
| Pino 35 | D3B — Channel B data bit 3 |
| Pino 36 | D4B — Channel B data bit 4 |
| Pino 37 | D5B — Channel B data bit 5 |
| Pino 38 | D6B — Channel B data bit 6 |
| Pino 39 | D7B — Channel B data bit 7 |
| Pino 40 | D8B — Channel B data bit 8 |
| Pino 41 | D9B — Channel B data bit 9 |
| Pino 42 | D10B — Channel B data bit 10 |
| Pino 43 | D11B — Channel B data bit 11 |
| Pino 44 | D12B — Channel B data bit 12 |
| Pino 45 | D13B — Channel B data bit 13 |
| Pino 46 | D14B — Channel B data bit 14 |
| Pino 47 | D15B — Channel B data bit 15 |
| Pino 48 | OF_B — Channel B data overflow flag |
| Pino 49 | CLKOUT_B — Channel B clock output / DCO |
| Pino 50 | OE — Output enable (active high) |
| Pino 51 | CS — SPI chip select (serial programming mode) |
| Pino 52 | SCK — SPI serial clock / LVDS configuration mode |
| Pino EP | GND — Exposed pad - thermal and ground, must be soldered to PCB ground plane |
Aplicações típicas
LTC2195IUKG é adequado para 6 aplicaçãos: Software-Defined Radio (SDR) Receiver, LTE / 3G Base-Station Digitizer, Test & Measurement Instrumentation, Medical Imaging Front-End, Diversity Receiver (Dual Antenna), Industrial Process-Control Data Acquisition.
Software-Defined Radio (SDR) Receiver
The LTC2195IUKG is well suited to software-defined radio receivers where two channels must capture phase-coherent I/Q baseband or a wideband IF. Its 125 Msps per channel lets designers digitize signals up to about 60 MHz of usable Nyquist bandwidth, while the dual simultaneous sampling enables I/Q demodulation without time-skew mismatch. The 76.8 dB SNR and 90 dB SFDR keep spurious tones well below the desired signal, and the 0.07 ps RMS aperture jitter permits accurate IF undersampling of carriers above the Nyquist frequency. The device's 535 mW total power draw keeps thermal budgets reasonable in portable or dense multi-channel receiver cards. Per the Analog Devices datasheet, this ADC pairs naturally with an FPGA or DSP that accepts CMOS, LVDS, or SPI data streams.
Recomendado
LTE / 3G Base-Station Digitizer
In LTE and 3G base-station receivers, the LTC2195IUKG digitizes wideband antenna signals while preserving the dynamic range needed for crest-factor reduction across many simultaneous users. The 76.8 dB SNR ensures that small uplink signals remain distinguishable from noise, and the 90 dB SFDR prevents intermodulation spurs from masking weaker users in adjacent resource blocks. Because the device samples at 125 Msps, a single ADC pair can capture a full 20 MHz LTE channel plus guard band with margin. The LVDS output mode reduces EMI in dense radio cards, an important consideration when many ADC channels sit near RF power amplifiers. Designers typically pair the part with a downstream FPGA running a CPRI or OBSAI framer.
Recomendado
Test & Measurement Instrumentation
Bench-top instruments such as digitizers, spectrum analyzers, and oscilloscope front-ends benefit from the LTC2195IUKG's combination of dual channels, 16-bit resolution, and 125 Msps throughput. The two simultaneous-sampling inputs allow direct capture of differential or complementary signals without external track-and-hold alignment. The pipelined core's wide input bandwidth suits the wideband IF strips used in modern vector signal analyzers. With 0.07 ps RMS aperture jitter, the device preserves phase accuracy for modulated measurements, and the 76.8 dB SNR provides enough headroom to characterize moderate-distortion devices on the bench. The 52-pin QFN 7x8 mm package simplifies integration into tight instrument front-end boards.
Recomendado
Medical Imaging Front-End
Ultrasound and other medical imaging front-ends use dual ADCs to capture returning echoes from paired transducer elements. The LTC2195IUKG's simultaneous-sampling dual channel architecture preserves the phase relationships needed for beamforming, while its 76.8 dB SNR ensures low-amplitude tissue echoes are not lost in quantization noise. Operating from a single 1.8 V supply, the part fits easily inside battery-powered portable ultrasound carts. The 0.07 ps RMS aperture jitter keeps timing accuracy high across fast pulse-echo sequences, which is essential for high-frame-rate imaging. The industrial -40C to +85C temperature rating covers the operating range of clinical equipment, including warmer sterilization-room environments.
Recomendado
Diversity Receiver (Dual Antenna)
Dual-antenna diversity receivers used in MIMO and antenna-combining systems require the two RF paths to be sampled with exact simultaneity so that the combiner sees a coherent snapshot. The LTC2195IUKG's pipelined architecture guarantees that both A and B channels convert on the same clock edge, eliminating the gain/phase mismatch that plagues time-interleaved designs. At 125 Msps per channel, designers can digitize 50+ MHz of instantaneous bandwidth per antenna with 16-bit headroom. The wide SFDR of 90 dB rejects intermodulation from out-of-band interferers common in dense urban deployments. The LVDS output mode is preferred in multi-channel diversity cards where many ADC traces would otherwise inject common-mode noise into sensitive RF sections.
Recomendado
Industrial Process-Control Data Acquisition
Process-control and condition-monitoring systems digitize vibration, acoustic, and current signals from industrial machinery to detect faults before catastrophic failure. The LTC2195IUKG provides two independent channels at 125 Msps, allowing simultaneous capture of, for example, vibration on a motor housing and current on the drive line, then post-processing for relative phase. With 76.8 dB SNR, the device captures the small dynamic signals of early-stage bearing wear, while the 0.07 ps RMS aperture jitter preserves the high-frequency harmonics that characterize imbalanced rotors. The -40C to +85C industrial temperature range covers factory-floor environments, and the 535 mW dissipation keeps the local thermal rise manageable inside sealed instrumentation housings.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para LTC2195IUKG — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | LTC2195CUKG | LTC2194IUKG | LTC2193IUKG | LTC2191IUKG | LTC2190IUKG |
|---|---|---|---|---|---|---|
| Package | 52-QFN (7x8 mm) | 52-QFN (7x8 mm) | 52-QFN (7x8 mm) | 52-QFN (7x8 mm) | 52-QFN (7x8 mm) | 52-QFN (7x8 mm) |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Sample Rate | 125 Msps | 125 Msps | 105 Msps | 80 Msps | 65 Msps | 50 Msps |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit |
| Channels | 2 simultaneous sampling | 2 simultaneous sampling | 2 simultaneous sampling | 2 simultaneous sampling | 2 simultaneous sampling | 2 simultaneous sampling |
| Temperature Grade | Industrial -40C to +85C | Commercial 0C to +70C | Industrial -40C to +85C | Industrial -40C to +85C | Industrial -40C to +85C | Industrial -40C to +85C |
| Digital Interface | Parallel / SPI / LVDS | Parallel / SPI / LVDS | Parallel / SPI / LVDS | Parallel / SPI / LVDS | Parallel / SPI / LVDS | Parallel / SPI / LVDS |
| Typical Power @ max rate | 535 mW | 535 mW | lower (105 Msps) | lower (80 Msps) | lower (65 Msps) | lower (50 Msps) |
Principais diferenciais
- Dual simultaneous sampling (vs LTC2180IUP)
- Pin compatibility across the LTC2195/2194/2193 speed grades (vs AD9268XCPZ-125 (cross-brand))
- Ultralow 0.07 ps RMS aperture jitter (vs LTC2174IUKG-14 (14-bit variant))
- 76.8 dB SNR and 90 dB SFDR (vs LTC2190IUKG (50 Msps family member))
Notas de projeto
The 52-pin QFN exposed pad MUST be soldered to a continuous PCB ground pour to keep junction temperature within spec. A floating or undersized thermal pad will cause the device to overheat at 125 Msps, especially inside a sealed enclosure. Recommended: at least 1 square cm of 1 oz copper tied to ground directly under EP, plus thermal vias to inner ground planes.
Per the Analog Devices datasheet, route analog input traces as 100-ohm differential pairs with controlled impedance, keep them short, and place input termination resistors within 5 mm of the AIN pins. Separate the analog and digital supplies with a ferrite bead and place the 1.8 V decoupling capacitors within 50 mils of the AVDD and OVDD pins to avoid coupling switching noise into the analog front end.
Drive the CLK input with a low-jitter, 50%-duty-cycle source. The LTC2195IUKG's 0.07 ps RMS aperture jitter is achievable only if the sample clock jitter is significantly below this figure; a noisy FPGA PLL clock can dominate the SNR floor and erase the device's 76.8 dB SNR advantage. Use a dedicated clock buffer and twisted-pair or stripline routing for the CLK line.
Avoid routing parallel-CMOS data buses through the analog input region. With LVDS enabled, route the LVDS pairs as 100-ohm matched pairs and length-match within 5 ps so that all bits arrive at the FPGA within one clock period. Where long output traces exist, place 100-ohm termination at the FPGA side, not at the ADC side, per LVDS best practice.
Informações de conformidade
Lead-free (PBF suffix) per Partstack listing 1869387330. RoHS compliant via the lead-free PBF ordering code; the standard LTC2195IUKG (non-PBF) lead finish is not RoHS. Halogen-free status not explicitly stated in the verified data.
