IRS21814MTRPBF vs IR2110SPBF Comparação
Comparação detalhada lado a lado de IRS21814MTRPBF por Infineon e IR2110SPBF por Infineon. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | IRS21814MTRPBF | IR2110SPBF |
|---|---|---|
| Marca | Infineon | Infineon |
| Categoria | Power MOSFET Drivers | Power MOSFET Drivers |
| Status do ciclo de vida | Ativo | Ativo |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $0,81 | $1,98 |
| Configuration | High and Low Side, Independent | — |
| Driver Channels | 2 (half-bridge) | — |
| Gate Drive Supply Voltage (VCC) | 10 V to 20 V | — |
| Floating Supply Voltage (VBS) | 10 V to 20 V (bootstrap) | — |
| Offset Voltage (High-Side) | Up to +600 V | — |
| Peak Source Current (typ.) | 1.9 A | — |
| Peak Sink Current (typ.) | 2.3 A | — |
| Logic Input Compatibility | 3.3 V and 5 V CMOS/LSTTL | 3.3 V CMOS / LSTTL |
| Propagation Delay (typ.) | 180 ns | — |
| Delay Matching (HS to LS) | [DATA_NEEDED: HS-LS delay matching spec] | — |
| Undervoltage Lockout | Yes (VCC and VBS) | — |
| dV/dt Immunity | Yes (negative-transient tolerant) | — |
| Encapsulamento | 16-MLPQ (4x4 mm) with Exposed Pad | 16-pin SOIC (SO-16, DW suffix) |
| Tipo de montagem | Surface Mount | Surface Mount |
| Temperatura de operação | -40C to +125C | — |
| Packaging | Tape & Reel | — |
| Status RoHS | Compliant | — |
| Função | — | Half-bridge gate driver |
| Topologia | — | High-side and low-side referenced output channels |
| Number of Channels | — | 2 (1 high-side, 1 low-side) |
| Logic Type | — | Non-inverting |
| Maximum Offset Voltage (Voffset) | — | 500 V |
| Gate Drive Supply Voltage (Vcc/VCC) | — | 10 V to 20 V |
| Peak Output Current (source/sink) | — | 2.0 A / 2.0 A |
| Typical Propagation Delay (ton/toff) | — | 94 ns / 94 ns |
| Rise/Fall Time (typical) | — | 25 ns / 17 ns |
| Bootstrap Diode | — | Integrated |
| Undervoltage Lockout (UVLO) | — | Yes, both Vcc and VCC |
| Faixa de temperatura de operação | — | -40 C to +125 C |
| Technology | — | HVIC + latch-immune CMOS |
| Lead-Free / RoHS | — | Yes / Compliant (Pb-free PBF suffix) |