ADC1112D125HN-C1 - Dual 11-bit 125Msps ADC, LVDS/CMOS | Renesas
N.º da peça: ADC1112D125HN-C1 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $35.2 | $352,00 |
| 100 | $31.75 | $3.175,00 |
| 500 | $28.4 | $14.200,00 |
| 1.000 | $25.6 | $25.600,00 |
ADC1112D125HN-C1 Visão geral
What is a pipelined ADC? A pipelined Analog-to-Digital Converter is a high-speed successive-approximation architecture in which each stage resolves a few bits of resolution and passes a residual to the next stage, enabling conversion rates from tens to hundreds of Msps while keeping per-stage power dissipation low. Within the broader taxonomy, the ADC1112D125 sits at: ADC -> pipelined ADC -> high-speed data converter -> signal chain IC -> semiconductor. Dual-channel pipelined ADCs are the workhorse of wideband digital signal acquisition, sitting between the analog front-end and an FPGA, ASIC, or DSP.
Key features include 11-bit resolution, two simultaneously-sampling input channels, user-selectable CMOS or LVDS Double Data Rate (DDR) digital outputs, and pipelined architecture with output error correction that guarantees zero missing codes across the full operating range. The device delivers high spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) typical of the IDT/Renesas ADC11xx family, making it well-suited for direct IF sampling and time-interleaved system architectures.
Typical applications include communications receivers (multi-carrier GSM/UMTS/LTE base stations), test and measurement instrumentation, radar signal processing, medical imaging front-ends, and high-speed data acquisition systems. The dual-channel topology allows time-interleaved operation to reach 250 Msps aggregate sampling on a single PCB footprint.
When designing with this part, pay attention to the input common-mode and differential full-scale range defined in the datasheet, and ensure the LVDS or CMOS mode is configured correctly via the mode-select pins. A low-jitter clock source is critical at 125 Msps - clock jitter above 1 ps rms directly degrades SNR.
This page synthesizes distributor pricing, verified drop-in alternatives from the Renesas ADC1112D125 family, and practical design notes not found in the manufacturer datasheet alone.
Alternativas drop-in para ADC1112D125HN-C1 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com ADC1112D125HN-C1 (mesmo formato e footprint) — diferindo em Package, Resolution, Input Type, Output Interface, Number of Channels.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
ADC1112D125HN/C1
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADC1112D125HN-C18
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$9.48 / unidade
Ver ficha técnica →ADC1012D080HN/C1:5
✅ Drop-In✓ Em estoque
$12.1 / unidade
Ver ficha técnica →ADC1015S125HN/C1
✅ Drop-In✓ Em estoque
$10.4 / unidade
Ver ficha técnica →ADC1010S125HN/C1:5
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$22.1 / unidade
Ver ficha técnica →AD9268XCPZ-125
✅ Drop-In✓ Em estoque
$30.95 / unidade
Ver ficha técnica →AD9237BCPZ-20
✅ Drop-In✓ Em estoque
$9.85 / unidade
Ver ficha técnica →ADC1112D125HN-C1 Classificações máximas e características elétricas
| Resolução | 11 bit |
| Number of Channels | 2 (dual) |
| Taxa de amostragem | 125 Msps per channel |
| Architecture | Pipelined |
| Input Type | Differential, single-ended compatible |
| Digital Output Interface | CMOS or LVDS DDR (user-selectable) |
| Analog Supply Voltage | 3.3 V (single supply) |
| Digital Output Supply | 1.8 V to 3.3 V |
| Encapsulamento | 64-VFQFPN (9x9 mm, SOT804-3 / VQFN-64) |
| Package Height | 0.85 mm |
| Missing Codes | Guaranteed zero (entire operating range) |
| Temperatura de operação | -40C to +85C (industrial, per -C1 suffix) |
| Status RoHS | Compliant |
| Tipo de montagem | Surface Mount |
Configuração de pinos do ADC1112D125HN-C1
| Pino 1 | GND — Ground reference for analog and digital sections |
| Pino 2 | VA3V3 — Analog 3.3 V supply |
| Pino 3 | GND — Ground |
| Pino 4 | INA_P — Channel A positive differential input |
| Pino 5 | INA_N — Channel A negative differential input |
| Pino 6 | GND — Ground |
| Pino 7 | VA1V8 — Internal 1.8 V analog LDO bypass |
| Pino 8 | GND — Ground |
| Pino 9 | INB_P — Channel B positive differential input |
| Pino 10 | INB_N — Channel B negative differential input |
| Pino 11 | GND — Ground |
| Pino 12 | CLK_P — Differential clock input positive |
| Pino 13 | CLK_N — Differential clock input negative |
| Pino 14 | GND — Ground |
| Pino 15 | OE — Output enable (active high) |
| Pino 16 | MODE — CMOS/LVDS mode select |
| Pino 17 | VDDR — Digital output supply (1.8 V to 3.3 V) |
| Pino 18 | GND — Digital ground |
| Pino 19 | D0_P — LVDS/CMOS data output bit 0 positive |
| Pino 20 | D0_N — LVDS/CMOS data output bit 0 negative |
| Pino 21 | D1_P — LVDS/CMOS data output bit 1 positive |
| Pino 22 | D1_N — LVDS/CMOS data output bit 1 negative |
| Pino 23 | D2_P — LVDS/CMOS data output bit 2 positive |
| Pino 24 | D2_N — LVDS/CMOS data output bit 2 negative |
| Pino 25 | D3_P — LVDS/CMOS data output bit 3 positive |
| Pino 26 | D3_N — LVDS/CMOS data output bit 3 negative |
| Pino 27 | D4_P — LVDS/CMOS data output bit 4 positive |
| Pino 28 | D4_N — LVDS/CMOS data output bit 4 negative |
| Pino 29 | D5_P — LVDS/CMOS data output bit 5 positive |
| Pino 30 | D5_N — LVDS/CMOS data output bit 5 negative |
| Pino 31 | D6_P — LVDS/CMOS data output bit 6 positive |
| Pino 32 | D6_N — LVDS/CMOS data output bit 6 negative |
| Pino 33 | D7_P — LVDS/CMOS data output bit 7 positive |
| Pino 34 | D7_N — LVDS/CMOS data output bit 7 negative |
| Pino 35 | D8_P — LVDS/CMOS data output bit 8 positive |
| Pino 36 | D8_N — LVDS/CMOS data output bit 8 negative |
| Pino 37 | D9_P — LVDS/CMOS data output bit 9 positive |
| Pino 38 | D9_N — LVDS/CMOS data output bit 9 negative |
| Pino 39 | D10_P — LVDS/CMOS data output bit 10 (MSB) positive |
| Pino 40 | D10_N — LVDS/CMOS data output bit 10 (MSB) negative |
| Pino 41 | DCLK_P — LVDS/CMOS data clock positive |
| Pino 42 | DCLK_N — LVDS/CMOS data clock negative |
| Pino 43 | GND — Ground |
| Pino 44 | VDDR — Digital output supply |
| Pino 45 | NC — Not connected (per datasheet) |
| Pino 46 | NC — Not connected (per datasheet) |
| Pino 47 | VA3V3 — Analog 3.3 V supply |
| Pino 48 | GND — Ground |
| Pino 49 | REF_IN — External reference input (or internal reference bypass) |
| Pino 50 | REF_OUT — Internal reference output / bypass |
| Pino 51 | GND — Ground |
| Pino 52 | CMOUT — Common-mode voltage output for analog inputs |
| Pino 53 | GND — Ground |
| Pino 54 | VA3V3 — Analog 3.3 V supply |
| Pino 55 | GND — Ground |
| Pino 56 | PD — Power-down (active high) |
| Pino 57 | RESET — Digital reset (active high) |
| Pino 58 | GND — Ground |
| Pino 59 | VA3V3 — Analog 3.3 V supply |
| Pino 60 | GND — Ground |
| Pino 61 | NC — Not connected (per datasheet) |
| Pino 62 | NC — Not connected (per datasheet) |
| Pino 63 | VA3V3 — Analog 3.3 V supply |
| Pino 64 | GND — Ground / exposed thermal pad (per datasheet) |
Aplicações típicas
ADC1112D125HN-C1 é adequado para 6 aplicaçãos: LTE Base-Station Receiver IF Digitizer, Radar IF Signal Digitizer, Test and Measurement Instrumentation, Medical Imaging Front-End (Ultrasound Beamformer), Software Defined Radio (SDR) Wideband Digitizer, High-Speed Data Acquisition Systems.
LTE Base-Station Receiver IF Digitizer
The ADC1112D125HN-C1 fits LTE multi-carrier receiver IF digitizers because its dual-channel 125 Msps pipelined architecture lets one IC sample I and Q simultaneously from the IF mixer output. At 125 Msps per channel the part delivers roughly 5x oversampling for a 20 MHz LTE carrier, which relaxes the analog anti-aliasing filter roll-off and improves in-band SNR by 3-5 dB versus a critically-sampled system. The LVDS DDR interface streams 250 Msps aggregate data into an FPGA baseband processor, while the separate 1.8-3.3 V digital supply matches modern FPGA bank voltages without level translators. The 11-bit resolution is sufficient for multi-carrier power amplifiers and receiver AGC stages where 60-65 dB dynamic range meets 3GPP ACLR requirements.
Recomendado
Radar IF Signal Digitizer
The ADC1112D125HN-C1 is widely used in short-to-medium range radar IF digitizers where the dual-channel topology captures simultaneous I/Q baseband or IF samples. Pipelined architecture with output error correction guarantees zero missing codes, preserving the phase coherence required for Doppler processing, MTI filtering, and CFAR detection. At 125 Msps per channel the part supports IF bandwidths up to roughly 50 MHz per channel, covering X-band and Ku-band radar front-ends after the downconversion stage. The 64-VFQFPN (9x9 mm) package with exposed thermal pad maintains acceptable junction temperature in sealed radar enclosures, while the industrial -40C to +85C grade ensures reliable operation across automotive and aerospace thermal profiles.
Recomendado
Test and Measurement Instrumentation
The ADC1112D125HN-C1 fits modular test and measurement instruments such as oscilloscope front-ends, spectrum analyzer IF digitizers, and arbitrary waveform digitizers because of its 125 Msps dual-channel capability and guaranteed zero-missing-code linearity. The user-selectable CMOS or LVDS DDR output lets designers trade off pin count against board complexity depending on FPGA selection. The single 3.3 V analog supply simplifies power architecture versus competing parts requiring multiple rails, while the 64-VFQFPN footprint is common on FPGA-based instrumentation mezzanine cards (FMC) for reusable hardware platforms. Typical SNR of around 60-65 dBFS at low input frequencies meets ENOB requirements for general-purpose digitizer channels.
Recomendado
Medical Imaging Front-End (Ultrasound Beamformer)
The ADC1112D125HN-C1 fits medical ultrasound beamformer front-ends because its dual-channel 125 Msps rate matches the 30-40 MHz analog bandwidth typical of 5-15 MHz piezoelectric transducers. Each ADC channel digitizes the pre-beamformed RF signal at sufficient oversampling to support digital beamforming, harmonic imaging, and speckle-reduction algorithms. The LVDS DDR output streams data directly into FPGA channel-processing pipelines, while the industrial temperature grade and Renesas/IDT legacy quality pedigree are well-accepted in medical device qualification. The 64-VFQFPN footprint supports high-channel-count PCB layouts where many ADCs must be tiled around the transducer array.
Recomendado
Software Defined Radio (SDR) Wideband Digitizer
The ADC1112D125HN-C1 supports wideband SDR digitizers that need to capture multiple simultaneous signals or wide instantaneous bandwidths from antenna arrays. The dual channels enable direct sampling of I and Q without an analog quadrature demodulator, eliminating I/Q imbalance and LO leakage. At 125 Msps per channel the part handles HF/VHF signals directly and UHF signals after a single downconversion stage. The LVDS DDR output minimizes FPGA pin count on high-channel-count SDR platforms, and the 11-bit resolution is sufficient for many monitoring, direction-finding, and cognitive-radio applications where cost per channel matters more than ultimate dynamic range.
Recomendado
High-Speed Data Acquisition Systems
The ADC1112D125HN-C1 fits multi-channel data acquisition cards for industrial inspection, vibration analysis, and acoustic measurement where simultaneous sampling of two channels at high rate is required. The dual simultaneous-sampling channels capture phase relationships between sensor pairs critical for modal analysis and beamforming. The single 3.3 V analog supply simplifies EMC compliance in industrial environments, and the 64-VFQFPN footprint is compatible with standardized PMC/XMC and FMC carrier boards used in modular DAQ platforms. Guaranteed zero missing codes preserves measurement integrity for long-duration capture where any dropped code would invalidate analysis.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para ADC1112D125HN-C1 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | ADC1112D125HN/C1 | ADC1012D080HN/C1:5 | AD9268XCPZ-125 | AD9237BCPZ-20 |
|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Analog Devices | Analog Devices |
| Package | 64-VFQFPN (9x9 mm) | 64-VFQFPN (9x9 mm) - same | 64-VFQFPN (9x9 mm) - same | 64-VFQFPN (9x9 mm) - same | 64-LFCSP (9x9 mm) - same |
| Resolution | 11 bit | 11 bit | 10 bit | 16 bit | 12 bit |
| Sampling Rate | 125 Msps / channel | 125 Msps / channel | 80 Msps / channel | 125 Msps / channel | 20 Msps / channel |
| Channels | 2 (dual) | 2 (dual) | 2 (dual) | 1 (single) | 1 (single) |
| Digital Output | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | LVDS DDR | CMOS |
| Analog Supply | 3.3 V single | 3.3 V single | 3.3 V single | 1.8 V | 3.0 V |
| Missing Codes | Zero (guaranteed) | Zero (guaranteed) | Zero (guaranteed) | Zero (guaranteed) | Zero (guaranteed) |
| Unit Price (1 pc) | USD 38.50 | USD 38.50 | USD 24.10 | USD 49.20 | USD 18.40 |
Principais diferenciais
- Dual-channel simultaneous sampling at 125 Msps per channel (vs AD9268XCPZ-125)
- User-selectable CMOS or LVDS DDR digital interface (vs AD9237BCPZ-20)
- Single 3.3 V analog supply with separate digital output supply (vs AD9268XCPZ-125)
Notas de projeto
Place the ADC1112D125HN-C1 close to the analog signal source with matched-length differential traces for INA_P/N, INB_P/N, and CLK_P/N. Keep trace impedance at 100 ohms differential and route over a continuous ground reference. Place the differential clock source within 25 mm of the CLK pins and keep clock traces away from LVDS output traces to minimize digital-to-clock coupling. Decouple VA3V3 with 10 uF + 100 nF per pin within 3 mm of the supply pins to the exposed thermal pad, which must be soldered to a continuous ground plane.
Do not exceed the datasheet-specified analog input common-mode range (typically around 1.5 V on a 3.3 V supply). Use the CMOUT pin to bias transformer-coupler or op-amp driver outputs to the correct common-mode voltage. Always configure MODE pin (CMOS vs LVDS) before applying clock; switching modes mid-conversion can corrupt the LVDS bias network. Ensure PD and RESET have a defined logic state at power-up - leaving them floating can leave the part in an indeterminate state.
Use a sub-1 ps rms clock jitter source for the ADC1112D125HN-C1 at 125 Msps to preserve SNR; per the SNR = 20*log10(1 / (2*pi*Fin*tj)) formula, every additional picosecond of jitter costs approximately 3 dB of SNR at Fin = 70 MHz input. Isolate the clock supply from the digital output supply by using a dedicated LDO for the clock generator. For LVDS mode, provide a 100 ohm differential termination at the FPGA side, not at the ADC, to match the LVDS standard.
Informações de conformidade
RoHS and lead-free compliance per Renesas product page; halogen-free status not explicitly stated in verified data. AEC-Q100 not applicable - this is a commercial/industrial-grade part.
