ADC1213D080HN-C18 - 12-bit 80MSPS Dual ADC with JESD204A | Renesas
N.º da peça: ADC1213D080HN-C18 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $34.65 | $346,50 |
| 100 | $29.9 | $2.990,00 |
| 500 | $25.4 | $12.700,00 |
| 1.000 | $21.75 | $21.750,00 |
ADC1213D080HN-C18 Visão geral
An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that samples continuous-time analog voltages and converts them into discrete digital codes at a specified sampling rate. Pipelined ADCs use a multi-stage architecture that enables high conversion throughput with moderate resolution (typically 8-14 bits) and low latency compared to delta-sigma converters. Within the broader IC taxonomy, this part belongs to the data converter family, which sits under signal chain ICs and broader mixed-signal power management and processing hierarchies used in modern electronic systems.
Key features of the ADC1213D080HN-C18 include 12-bit resolution, 80 MSPS sampling per channel, dual simultaneous sampling inputs, JESD204A serial interface with up to 3.125 Gbps lane rates, integrated input buffer, and SPI-compatible configuration registers. The pipelined architecture provides 6-7 effective bits of ENOB at high input frequencies, making it suitable for wideband IF sampling in software-defined architectures. The device supports both single-ended and differential analog inputs with flexible common-mode adjustment.
Typical applications include multi-antenna wireless receiver baseband, software-defined radio (SDR) platforms, cable modem downstream capture, radar signal processing front-ends, medical imaging digitizers, and broadband test and measurement equipment. The dual-channel matched sampling characteristic is particularly valuable in I/Q demodulation paths and diversity receivers where channel-to-channel gain and offset matching directly impact demodulation accuracy.
When designing with this part, ensure the JESD204A link parameters (L, M, F, K, and N) are correctly programmed to match the receiving FPGA or ASIC. Proper decoupling of the 1.8 V AVDD and 3.3 V DRVDD rails, along with careful PCB layout of the high-speed CML serial outputs, is critical to achieving the rated BER performance on the JESD204A link.
Alternativas drop-in para ADC1213D080HN-C18 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com ADC1213D080HN-C18 (mesmo formato e footprint) — diferindo em Package, Input Type, Number of Channels, Resolution, MSL Level.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
ADC1213D080HN/C18
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADC1213D125HN-C18
✅ Drop-In✓ Em estoque
$30.5 / unidade
Ver ficha técnica →ADC1213D065HN-C18
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
ADC1012D080HN/C1:5
✅ Drop-In✓ Em estoque
$12.1 / unidade
Ver ficha técnica →ADC1112D125HN-C18
✅ Drop-In✓ Em estoque
$9.48 / unidade
Ver ficha técnica →ADC1015S125HN/C1
✅ Drop-In✓ Em estoque
$10.4 / unidade
Ver ficha técnica →ADS62P23IRGC25
✅ Drop-In✓ Em estoque
$18.85 / unidade
Ver ficha técnica →ADC1213D080HN-C18 Classificações máximas e características elétricas
| Resolução | 12 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sampling Rate per Channel | 80 MSPS |
| Architecture | Pipelined |
| Data Output Interface | JESD204A (serial, up to 3.125 Gbps lane) |
| Encapsulamento | 56-VFQFPN exposed pad (8x8 mm) |
| Analog Supply Voltage (AVDD) | 1.8 V |
| Digital/Drive Supply Voltage (DRVDD) | 3.3 V |
| Input Type | Differential / single-ended (configurable) |
| Faixa de temperatura de operação | -40 C to +85 C (industrial) |
| Configuration Interface | SPI-compatible serial |
| Tipo de montagem | Surface Mount |
| Nível MSL | 3 (per JEDEC J-STD-020) |
| Status RoHS | Compliant |
| Lead-Free | Yes |
Configuração de pinos do ADC1213D080HN-C18
| Pino 1 | INA_P — Channel 1 positive analog input |
| Pino 2 | INA_N — Channel 1 negative analog input |
| Pino 3 | AVDD — 1.8 V analog supply |
| Pino 4 | GND — Ground |
| Pino 5 | CLK_P — Differential clock positive |
| Pino 6 | CLK_N — Differential clock negative |
| Pino 7 | VCM — Common-mode voltage output |
| Pino 8 | REF — Reference voltage bypass |
| Pino 9 | AVDD — 1.8 V analog supply |
| Pino 10 | GND — Ground |
| Pino 11 | INB_P — Channel 2 positive analog input |
| Pino 12 | INB_N — Channel 2 negative analog input |
| Pino 13 | AVDD — 1.8 V analog supply |
| Pino 14 | GND — Ground |
| Pino 15 | SENSE — Reference mode select |
| Pino 16 | AVDD — 1.8 V analog supply |
| Pino 17 | GND — Ground |
| Pino 18 | NC — Not connected |
| Pino 19 | NC — Not connected |
| Pino 20 | RESETB — Active-low reset |
| Pino 21 | SDIO — SPI serial data I/O |
| Pino 22 | SCLK — SPI serial clock |
| Pino 23 | CSB — SPI chip select (active low) |
| Pino 24 | DRVDD — 3.3 V digital supply |
| Pino 25 | GND — Ground |
| Pino 26 | SYNCB — JESD204A sync request |
| Pino 27 | DRVDD — 3.3 V digital supply |
| Pino 28 | GND — Ground |
| Pino 29 | OUT0_P — JESD204A lane 0 positive |
| Pino 30 | OUT0_N — JESD204A lane 0 negative |
| Pino 31 | GND — Ground |
| Pino 32 | DRVDD — 3.3 V digital supply |
| Pino 33 | GND — Ground |
| Pino 34 | NC — Not connected |
| Pino 35 | NC — Not connected |
| Pino 36 | DRVDD — 3.3 V digital supply |
| Pino 37 | GND — Ground |
| Pino 38 | NC — Not connected |
| Pino 39 | NC — Not connected |
| Pino 40 | NC — Not connected |
| Pino 41 | NC — Not connected |
| Pino 42 | AVDD — 1.8 V analog supply |
| Pino 43 | GND — Ground |
| Pino 44 | NC — Not connected |
| Pino 45 | NC — Not connected |
| Pino 46 | NC — Not connected |
| Pino 47 | NC — Not connected |
| Pino 48 | NC — Not connected |
| Pino 49 | NC — Not connected |
| Pino 50 | NC — Not connected |
| Pino 51 | NC — Not connected |
| Pino 52 | NC — Not connected |
| Pino 53 | NC — Not connected |
| Pino 54 | NC — Not connected |
| Pino 55 | NC — Not connected |
| Pino 56 | EP — Exposed pad (thermal/ground) |
Aplicações típicas
ADC1213D080HN-C18 é adequado para 6 aplicaçãos: Multi-Antenna Wireless Receiver Baseband, Software-Defined Radio (SDR) Platforms, Cable Modem Downstream Capture, Radar Signal Processing Front-End, Medical Imaging Digitizers (Ultrasound/Portable Object), Broadband Test and Measurement Equipment.
Multi-Antenna Wireless Receiver Baseband
The ADC1213D080HN-C18's dual simultaneous-sampling 12-bit 80 MSPS channels and JESD204A serial output make it a strong fit for multi-antenna wireless receiver baseband digitizers. Each antenna's I/Q baseband or IF signal can be captured by one channel with matched gain and offset, critical for beamforming and diversity combining where channel-to-channel mismatch degrades SNR. The 80 MSPS rate supports signal bandwidths up to ~30 MHz per channel, covering LTE, Wi-Fi, and 5G NR FR1 allocations. The JESD204A interface aggregates both channels over a single lane up to 3.125 Gbps, eliminating the parallel LVDS routing congestion typical of older dual ADCs. Place the ADC adjacent to the antenna LNA/Mixer chain with controlled-impedance differential traces; bypass AVDD with 10uF + 0.1uF ceramics as close to the supply pins as possible.
Recomendado
Software-Defined Radio (SDR) Platforms
The ADC1213D080HN-C18 is purpose-built for SDR platforms where software reconfigurability across multiple waveforms is required. Its 12-bit resolution provides ~70 dB SNR at low IF, enabling demodulation of complex modulation schemes (QPSK, 16-QAM, 64-QAM) without SNR-limited symbol errors. The dual-channel architecture supports full I/Q capture from a quadrature demodulator in a single IC, reducing board area and BOM cost versus two single-channel ADCs. At 80 MSPS the part handles IF bandwidths typical of HF/VHF/UHF ham radio, public safety radio, and tactical communications. The JESD204A link connects directly to modern FPGAs (Xilinx 7-series, Intel Cyclone V) that run the SDR baseband DSP. Power consumption is moderate; provide a 4-layer PCB with continuous ground plane under the exposed pad for thermal dissipation.
Recomendado
Cable Modem Downstream Capture
The ADC1213D080HN-C18 is well-suited for DOCSIS downstream capture in cable modem head-end and CMTS equipment. Cable downstream signals occupy 6 MHz (DOCSIS 3.0) or up to 192 MHz (DOCSIS 3.1 OFDM) bandwidths, well within the 30+ MHz per-channel capability of an 80 MSPS ADC. The dual-channel architecture allows capture of two downstream channels or one channel plus a monitoring tap. The JESD204A serial interface simplifies the backplane connection to the upstream MAC/PHY ASIC. The 1.8V analog supply operates from standard cable modem bus voltages, simplifying power tree design. Use a transformer-coupled input network to interface with the 75-ohm coax; the ADC's differential inputs reject common-mode noise from the cable plant.
Recomendado
Radar Signal Processing Front-End
The ADC1213D080HN-C18 fits medium-bandwidth radar front-end digitizers such as those in automotive radar (76-81 GHz with sub-IF sampling), perimeter surveillance radar, and weather radar I/Q baseband. The dual-channel simultaneous sampling is essential for I/Q demodulation of the radar IF, preserving phase information used for target ranging and Doppler extraction. 12-bit resolution provides ~72 dB dynamic range, sufficient for separating targets from clutter in typical radar scenarios. At 80 MSPS per channel, baseband bandwidths up to 30 MHz support most pulsed and FMCW radar waveforms. The JESD204A interface delivers both I and Q streams over a single high-speed lane to the radar signal processor FPGA/ASIC. The exposed pad enables direct PCB heatsinking for continuous operation.
Recomendado
Medical Imaging Digitizers (Ultrasound/Portable Object)
The ADC1213D080HN-C18 serves ultrasound beamformer front-ends and other medical imaging digitizers where moderate-resolution, multi-channel sampling is required. Each ultrasound channel requires matched I/Q or RF sampling; the dual-channel ADC1213D8010 reduces the channel count of ADCs needed for a 64- or 128-channel beamformer, saving PCB area and power. The 12-bit resolution is sufficient for B-mode ultrasound envelope detection. The JESD204A serial interface aggregates channels efficiently to the beamforming FPGA. The industrial -40 to +85 C temperature range supports operation near the transducer array where temperatures can elevate. Observe IEC 60601-1 medical safety isolation requirements for the analog input network.
Recomendado
Broadband Test and Measurement Equipment
The ADC1213D080HN-C18 is used in broadband oscilloscopes, spectrum analyzers, and signal analyzer digitizer front-ends. The 80 MSPS per-channel rate suits mid-band oscilloscope channels (50-100 MHz bandwidth class) where 12-bit vertical resolution provides 4x more dynamic range than typical 8-bit scope ADCs. The matched dual-channel architecture enables two scope channels from a single IC, useful for 2-channel portable scopes. The JESD204A interface delivers samples to the scope FPGA/ASIC for display and triggering. Per Renesas datasheet, the differential inputs reject common-mode noise from the probe ground path. Use a front-end attenuator/buffer network to scale input voltages to the ADC's full-scale range; the exposed pad requires direct PCB soldering for thermal dissipation during continuous sampling.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para ADC1213D080HN-C18 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | ADC1213D080HN/C18 | ADC1213D125HN-C18 | ADC1213D065HN-C18 | ADC1012D080HN/C1:5 | ADS62P23IRGC25 |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Texas Instruments |
| Package | 56-VFQFPN (8x8 mm) | 56-VFQFPN (8x8 mm) - same | 56-VFQFPN (8x8 mm) - same | 56-VFQFPN (8x8 mm) - same | 56-VFQFPN (8x8 mm) - same | 64-VQFN (different VQFN) |
| Resolution | 12 bit | 12 bit - same | 12 bit - same | 12 bit - same | 10 bit -2 bits | 12 bit - same |
| Channels | 2 | 2 - same | 2 - same | 2 - same | 2 - same | 2 - same |
| Sampling Rate | 80 MSPS/ch | 80 MSPS/ch - same | 125 MSPS/ch +56% | 65 MSPS/ch -19% | 80 MSPS/ch - same | 65 MSPS/ch -19% |
| Architecture | Pipelined | Pipelined - same | Pipelined - same | Pipelined - same | Pipelined - same | Pipelined - same |
| Data Interface | JESD204A | JESD204A - same | JESD204A - same | JESD204A - same | JESD204A - same | Parallel LVDS - different |
| Analog Supply | 1.8 V | 1.8 V - same | 1.8 V - same | 1.8 V - same | 1.8 V - same | 3.3 V - different |
Principais diferenciais
- Highest resolution in dual ADC1213 family at 80 MSPS (vs ADC1012D080HN/C1:5)
- Higher sample rate than dual ADC1010/1012 family (vs ADC1012D080HN/C1:5)
- JESD204A serial interface vs parallel LVDS (vs ADS62P23IRGC25)
- Lower power consumption vs higher-speed parts (vs ADC1213D125HN-C18)
Notas de projeto
Use a 4-layer PCB with continuous ground plane under the 56-VFQFPN exposed pad. Solder the exposed pad (pin 56) to a 5x5 mm copper pad with at least 9 thermal vias (0.3 mm drill, 0.6 mm pitch) to the inner ground plane. Route the differential analog inputs (INA_P/INA_N, INB_P/INB_N) as 100-ohm differential microstrip on the top layer with no splits in the reference plane beneath. Place 10uF X7R ceramic + 0.1uF NP0/C0G ceramics within 2 mm of each AVDD pin; use ferrite beads to isolate analog and digital grounds at the supply entry point. The JESD204A CML outputs (OUT0_P/N) require 100-ohm differential routing with length matching to within 1 mm.
Drive the differential clock inputs (CLK_P/CLK_N) with a low-jitter clock driver (jitter <300 fs RMS) such as an LMX2541 or equivalent. AC-couple the clock inputs with 0.1uF capacitors close to the ADC pins if using single-ended clock sources. The JESD204A link requires deterministic latency subclass 1 with SYSREF for multi-device synchronization; pull SYSREF through the FPGA or ASIC clock generation logic. Verify link BER with built-in PRBS patterns before enabling functional data capture. Keep analog input traces away from digital output traces by at least 3 mm or guard with ground via fences to prevent coupling.
Do not float the SENSE pin - tie it to GND for internal reference mode or to AVDD for external reference mode. The REF pin requires a 10uF X7R bypass capacitor directly to ground, not through ferrite beads. Power-up sequence: bring up DRVDD (3.3 V) first, then AVDD (1.8 V); failure to follow may trigger ESD protection diodes. Do not exceed the 2.0 V absolute maximum on any analog input; use a front-end protection network if the input can see transients. Estimated: at 80 MSPS full-rate dual channel, junction temperature rise is ~15-20 C above ambient with proper PCB layout (per typical Renesas datasheet thermal data) - verify with on-board thermistor in production.
Informações de conformidade
RoHS and REACH compliant per Renesas product page. Industrial temperature grade (-40 to +85 C); not AEC-Q100 qualified for automotive - contact Renesas for automotive-grade equivalents in the ADC1213 family.
