CDK2307DILP64 - Dual 13-bit 80MSPS ADC | Cadeka/MaxLinear QFN-64
N.º da peça: CDK2307DILP64 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $18.45 | $18,45 |
| 10 | $16.8 | $168,00 |
| 100 | $14.25 | $1.425,00 |
| 500 | $12.1 | $6.050,00 |
| 1.000 | $10.4 | $10.400,00 |
CDK2307DILP64 Visão geral
An ADC (Analog-to-Digital Converter) is a data converter that samples continuous analog signals and produces discrete digital codes. Within the data-converter hierarchy, the CDK2307DILP64 sits in the pipelined-ADC subfamily, which is the dominant architecture for sample rates between 5 MSPS and 250 MSPS because it balances high sample rate, moderate resolution, and low power per conversion. Pipelined ADCs are widely used in communications, medical imaging, instrumentation, and defense systems where a multi-MHz analog front-end must be digitized with 10-14 bit effective resolution.
Key features of the CDK2307DILP64 include user-selectable 12-bit or 13-bit resolution, four speed grades (20/40/65/80 MSPS) shared across the family, a single-ended analog input, parallel CMOS output bus, and an internal bandgap reference. The dual-channel integration saves board area versus two discrete ADCs while maintaining channel-to-channel matching for time-interleaved or I/Q demodulation architectures. The 64-pin QFN package exposes a thermal pad, supporting the ~200 mW total dissipation without requiring an external heatsink.
The pipelined core uses a multi-stage switched-capacitor architecture with per-stage MDAC gain of 2 and digital error correction, yielding low DNL and INL. The internal reference simplifies BOM cost, while a separate REFIN pin allows the user to drive an external reference for gain calibration or ratio-metric measurements. The CMOS output bus reduces digital switching noise on the supply rails, easing layout in mixed-signal designs.
Typical applications include communications I/Q baseband digitization, multi-channel data acquisition cards, medical ultrasound beamformers, handheld test instrumentation, and industrial inspection imaging. Its dual channels suit diversity receivers, simultaneous-sample vibration analysis, and any design where PCB area or channel-to-channel skew is critical.
When designing with this part, place the analog and digital supplies on separate PCB planes joined at a single ferrite bead near the IC, and bypass each supply pin with a 100 nF X7R capacitor within 2 mm of the pad. Use the exposed pad as the primary thermal and ground return path; failing to solder it degrades electrical and thermal performance.
This page synthesizes distributor pricing, drop-in alternatives, and practical layout notes not consolidated on the manufacturer datasheet, giving engineers a faster starting point for dual-channel 80 MSPS designs.
Alternativas drop-in para CDK2307DILP64 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com CDK2307DILP64 (mesmo formato e footprint) — diferindo em Manufacturer, Package, Reference, Resolution, Input Type.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
CDK2307CILP40
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
CDK2307AILP64
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$7.1 / unidade
Ver ficha técnica →CDK1307CILP40
✅ Drop-In✓ Em estoque
$3.95 / unidade
Ver ficha técnica →CDK2307DILP64 Classificações máximas e características elétricas
| Manufacturer | Cadeka Microcircuits (now MaxLinear) |
| Função | Dual Analog-to-Digital Converter |
| Resolução | 12-bit / 13-bit (user selectable) |
| Number of Channels | 2 (dual) |
| Taxa de amostragem | 20 / 40 / 65 / 80 MSPS (family-wide) |
| Input Type | Single-Ended |
| Output Interface | Parallel CMOS |
| Analog Supply Voltage | 1.7 V to 3.6 V |
| Digital Supply Voltage | 1.7 V to 3.6 V |
| Power Consumption | 102 mW per channel at 80 MSPS |
| Reference | Internal bandgap (external REFIN supported) |
| Architecture | Pipelined with digital error correction |
| Encapsulamento | QFN-64 (7 mm x 7 mm) with exposed pad |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant (per distributor listings) |
Configuração de pinos do CDK2307DILP64
| Pino 1 | AIN1+ — Channel 1 positive analog input |
| Pino 2 | AIN1- — Channel 1 negative analog input (or ground for single-ended) |
| Pino 3 | AVDD — Analog supply voltage (1.7 V to 3.6 V) |
| Pino 4 | AVSS — Analog ground |
| Pino 5 | REFIN — External reference input (bypass with capacitor to AVSS if internal reference used) |
| Pino 6 | REFOUT — Internal reference output (bypass with capacitor to AVSS) |
| Pino 7 | VCM — Common-mode voltage output (bypass with capacitor to AVSS) |
| Pino 8 | AVSS — Analog ground |
| Pino 9 | AVDD — Analog supply voltage |
| Pino 10 | CLK+ — Differential clock positive input |
| Pino 11 | CLK- — Differential clock negative input |
| Pino 12 | DVDD — Digital supply voltage (1.7 V to 3.6 V) |
| Pino 13 | DVSS — Digital ground |
| Pino 14 | CSB — Chip select bar (active low, CMOS control interface) |
| Pino 15 | SCLK — Serial clock for CMOS control interface |
| Pino 16 | SDIO — Serial data input/output for control interface |
| Pino 17 | RESETB — Reset bar (active low) |
| Pino 18 | PD — Power-down control input |
| Pino 19 | OE — Output enable for parallel data bus |
| Pino 20 | D0 — CMOS data output bit 0 (LSB) |
| Pino 21 | D1 — CMOS data output bit 1 |
| Pino 22 | D2 — CMOS data output bit 2 |
| Pino 23 | D3 — CMOS data output bit 3 |
| Pino 24 | D4 — CMOS data output bit 4 |
| Pino 25 | D5 — CMOS data output bit 5 |
| Pino 26 | D6 — CMOS data output bit 6 |
| Pino 27 | D7 — CMOS data output bit 7 |
| Pino 28 | D8 — CMOS data output bit 8 |
| Pino 29 | D9 — CMOS data output bit 9 |
| Pino 30 | D10 — CMOS data output bit 10 |
| Pino 31 | D11 — CMOS data output bit 11 |
| Pino 32 | D12 — CMOS data output bit 12 (MSB in 13-bit mode) |
| Pino 33 | DVDD — Digital supply voltage |
| Pino 34 | DVSS — Digital ground |
| Pino 35 | NC — Not connected (per datasheet) |
| Pino 36 | NC — Not connected (per datasheet) |
| Pino 37 | DORA — Data output rate A (channel 1 data ready) |
| Pino 38 | DORB — Data output rate B (channel 2 data ready) |
| Pino 39 | AVDD — Analog supply voltage |
| Pino 40 | AVSS — Analog ground |
| Pino 41 | AIN2+ — Channel 2 positive analog input |
| Pino 42 | AIN2- — Channel 2 negative analog input (or ground for single-ended) |
| Pino 43 | AVSS — Analog ground |
| Pino 44 | AVDD — Analog supply voltage |
| Pino 45 | VREF — Reference voltage decoupling node |
| Pino 46 | NC — Not connected (per datasheet) |
| Pino 47 | NC — Not connected (per datasheet) |
| Pino 48 | DVDD — Digital supply voltage |
| Pino 49 | DVSS — Digital ground |
| Pino 50 | D12B — Channel 2 data output bit 12 (MSB) |
| Pino 51 | D11B — Channel 2 data output bit 11 |
| Pino 52 | D10B — Channel 2 data output bit 10 |
| Pino 53 | D9B — Channel 2 data output bit 9 |
| Pino 54 | D8B — Channel 2 data output bit 8 |
| Pino 55 | D7B — Channel 2 data output bit 7 |
| Pino 56 | D6B — Channel 2 data output bit 6 |
| Pino 57 | D5B — Channel 2 data output bit 5 |
| Pino 58 | D4B — Channel 2 data output bit 4 |
| Pino 59 | D3B — Channel 2 data output bit 3 |
| Pino 60 | D2B — Channel 2 data output bit 2 |
| Pino 61 | D1B — Channel 2 data output bit 1 |
| Pino 62 | D0B — Channel 2 data output bit 0 (LSB) |
| Pino 63 | OEB — Output enable for channel 2 data bus |
| Pino 64 | MODE — Resolution mode select (12-bit or 13-bit) |
Aplicações típicas
CDK2307DILP64 é adequado para 7 aplicaçãos: Communications I/Q Baseband Digitization, Multi-Channel Data Acquisition Cards, Medical Ultrasound Beamforming, Handheld Test and Measurement Instrumentation, Industrial Inspection Imaging Systems, Radar and Lidar Baseband Receivers, Software Defined Radio Front-End.
Communications I/Q Baseband Digitization
The CDK2307DILP64 is well-suited to communications I/Q baseband digitization. Its dual 13-bit 80 MSPS channels allow direct sampling of low-IF or zero-IF signals from a quadrature demodulator, and the matched channel-to-channel gain/offset of an integrated dual ADC preserves I/Q image rejection better than two discrete ADCs. Placed after the AGC stage with the analog inputs AC-coupled through 0.1 uF capacitors, the parallel CMOS output bus feeds an FPGA or baseband DSP with one clock cycle of latency, supporting LTE, Wi-Fi, and proprietary radio receivers. The 1.7-3.6 V analog supply range simplifies interface to common 1.8 V or 3.3 V RF front-end ICs. The 102 mW per channel power at 80 MSPS allows fan-less radio designs in compact enclosure formats.
Recomendado
Multi-Channel Data Acquisition Cards
For multi-channel DAQ cards in PCI/PCIe or PXI form factors, the CDK2307DILP64 integrates two matched 13-bit 80 MSPS converters in a 7x7 mm QFN-64 footprint, reducing PCB area versus two discrete ADCs. Each channel's internal bandgap reference and digital error correction yield low DNL/INL suitable for vibration analysis, sonar beamforming, and laboratory instrumentation. The parallel CMOS output bus is compatible with FPGA-based capture engines, and the exposed thermal pad supports continuous 80 MSPS operation without external heatsinking. Operating from a 1.8 V or 3.3 V analog supply, the part integrates cleanly with downstream LVDS serializers for high-channel-count systems requiring fewer PCB traces to the host controller.
Recomendado
Medical Ultrasound Beamforming
In medical ultrasound systems, the CDK2307DILP64's dual-channel 80 MSPS architecture is appropriate for receive-channel beamforming front-ends where adjacent channels require tight gain and phase matching. The 13-bit resolution over 80 MSPS provides dynamic range adequate for tissue harmonic imaging, and the 1.7-3.6 V supply range simplifies integration with low-voltage LNA and TGC stages. Each channel's parallel CMOS output interfaces with delay-line FPGAs, and the small 7x7 mm QFN-64 package allows 32-64 channel beamformer boards to fit within hand-held probe enclosures. Internal digital error correction maintains channel-to-channel matching within +/-1 LSB over the operating temperature range.
Recomendado
Handheld Test and Measurement Instrumentation
For portable oscilloscopes, logic analyzers, and spectrum-analyzer front-ends, the CDK2307DILP64 dual 13-bit 80 MSPS capability captures repetitive or single-shot waveforms with 13 effective bits at moderate analog input bandwidths. The 102 mW per channel power consumption supports battery-powered operation for hours, and the small QFN-64 footprint allows integration into handheld plastic enclosures. The internal bandgap reference eliminates an external reference IC, reducing BOM cost. The parallel CMOS output bus drives FPGA capture memory with deterministic one-cycle latency, supporting real-time trigger and measurement features. The exposed thermal pad permits direct PCB mounting without a heatsink at full 80 MSPS operation in still air.
Recomendado
Industrial Inspection Imaging Systems
In industrial X-ray, optical inspection, and machine-vision line-scan cameras, the CDK2307DILP64 dual 13-bit 80 MSPS channels can digitize two synchronized line-scan sensors or a stereo vision pair. The matched channel characteristics ensure calibrated image pairs, and the 1.7-3.6 V analog supply range operates from 3.3 V rails common in industrial cameras. The internal reference and digital error correction reduce factory calibration steps, while the QFN-64 package's small footprint supports 2-channel camera head boards with tight mechanical envelopes. The parallel CMOS output bus interfaces with image FPGAs that perform real-time processing for defect detection, and the 102 mW per channel dissipation is manageable without active cooling in IP65-rated enclosures.
Recomendado
Radar and Lidar Baseband Receivers
For automotive radar, lidar, and surveillance radar baseband receivers, the CDK2307DILP64 dual 13-bit 80 MSPS channels digitize I and Q baseband signals from a single radar front-end. The matched channel-to-channel gain/offset of the integrated dual converter preserves phase coherence between I and Q paths, which is critical for FFT-based Doppler processing. Operating from a 1.8 V or 3.3 V analog supply, the part interfaces directly with low-voltage radar MMIC outputs. The 102 mW per channel power at 80 MSPS allows 12V-rail automotive designs without active cooling, and the small 7x7 mm QFN-64 footprint supports integration into compact radar ECU modules. The exposed thermal pad provides adequate heat spreading for continuous-wave radar duty cycles.
Recomendado
Software Defined Radio Front-End
In software defined radio platforms, the CDK2307DILP64's dual 13-bit 80 MSPS channels allow direct sampling of low-IF or zero-IF signals covering amateur, marine, and shortwave bands. The parallel CMOS output bus feeds an FPGA running GNU Radio or vendor DSP frameworks, with deterministic one-cycle latency supporting real-time demodulation. The internal bandgap reference reduces external components, and the 1.7-3.6 V supply range allows operation from common 3.3 V SDR board rails. The 7x7 mm QFN-64 footprint is small enough for integration into SDR front-end cards with multiple ADCs, and the 102 mW per channel power dissipation is consistent with fan-less SDR enclosures. Channel matching within +/-1 LSB supports calibrated I/Q demodulation for digital modulation schemes.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para CDK2307DILP64 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | CDK2307CILP40 | CDK2307AILP64 | CDK1307CILP40 |
|---|---|---|---|---|
| Brand | MaxLinear (Cadeka) | MaxLinear (Cadeka) | MaxLinear (Cadeka) | MaxLinear (Cadeka) |
| Package | QFN-64 (7x7 mm) | QFN-64 (7x7 mm) - same | QFN-64 (7x7 mm) - same | QFN-64 (7x7 mm) - same |
| Resolution | 12 / 13-bit selectable | 12 / 13-bit selectable | 12 / 13-bit selectable | 12 / 13-bit selectable |
| Sample Rate (max) | 80 MSPS | 80 MSPS | 80 MSPS | 40 MSPS (-50%) |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Analog Supply | 1.7 V to 3.6 V | 1.7 V to 3.6 V | 1.7 V to 3.6 V | 1.7 V to 3.6 V |
| Power per Channel at Max Rate | 102 mW | 102 mW | 102 mW | ~55 mW at 40 MSPS |
| Output Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS |
| Operating Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Automotive (-40C to +125C) | Commercial (0C to +70C) |
Principais diferenciais
- Integrated dual 13-bit 80 MSPS ADC in QFN-64 (vs ADS6425IRGCR (TI 12-bit 105 MSPS quad))
- Internal bandgap reference with external override (vs AD9268XCPZ-125 (16-bit 125 MSPS dual))
- QFN-64 with integrated exposed thermal pad (vs CDK1307CILP40 (40 MSPS lower-speed sibling))
Notas de projeto
Estimated: at 80 MSPS the CDK2307DILP64 draws ~204 mW total from AVDD plus ~10-15 mW from DVDD. Use a ferrite bead between AVDD and DVDD rails joined at a single star point near the IC, with a 10 uF bulk and 100 nF X7R bypass within 2 mm of each AVDD pin. Keep the analog supply LDO or filter network within 25 mm of the IC to minimize IR drop and high-frequency noise injection into the reference. The internal bandgap reference draws current proportional to sample rate; bypass REFOUT with a 1 uF X7R capacitor.
Place all four AVDD and all four DVDD bypass capacitors within 2 mm of their respective pins with vias to a solid ground plane on the layer immediately below. The exposed thermal pad must be soldered to a continuous ground pour with a 4x4 via array to the inner ground plane for thermal dissipation and low-inductance ground return. Separate the analog input traces from the parallel CMOS output bus with a ground guard trace to prevent digital switching noise from coupling into the analog front-end.
Drive the CLK+/CLK- differential input with a low-jitter clock source; jitter directly degrades SNR according to SNR = 6.02 * ENOB + 1.76 + 10*log10(FSR/2*pi*fin*tjitter). For 13 effective bits at 70 MHz analog input, target a clock source jitter under 1 ps RMS. The parallel CMOS output bus has 13 lines per channel toggling at the sample rate - route them on the inner layers with controlled 50 ohm impedance and source-terminate near the ADC if the FPGA is more than 50 mm away.
Do not leave the REFOUT pin unbypassed - the internal reference will oscillate and corrupt conversion accuracy. Do not apply an analog input before the AVDD rail reaches at least 1.5 V; the input ESD structures can latch. Use a single solid ground plane, not a split ground, because the exposed pad serves as the primary ground return and any discontinuity degrades both electrical and thermal performance. Always operate within the datasheet's common-mode input range; signals outside VCM +/- 0.5 V cause distortion.
Estimated: total package dissipation at 80 MSPS is approximately 215 mW. With the QFN-64 7x7 mm exposed pad soldered to a 4x4 via array ground pour on a 4-layer 1 oz copper PCB, theta_JA is approximately 28 C/W, yielding a junction temperature rise of 6 C above ambient. At 70 C ambient the junction sits at 76 C, well below the 150 C maximum. For continuous operation above 85 C ambient, add a top-side copper pour connected by thermal vias to maximize heat spreading.
Informações de conformidade
RoHS compliance confirmed by distributor listings (Mouser, Octopart). Industrial temperature grade - not AEC-Q100 qualified; for automotive applications use CDK2307AILP64 variant. Halogen-free status not explicitly stated in available data; recommend contacting MaxLinear for confirmation.
