DS90UB947TRGCRQ1 - 1080p oLDI Dual FPD-Link III Serializer | TI
N.º da peça: DS90UB947TRGCRQ1 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $11.42 | $11,42 |
| 10 | $10.3 | $103,00 |
| 100 | $9.18 | $918,00 |
| 500 | $8.1 | $4.050,00 |
| 1.000 | $7.35 | $7.350,00 |
DS90UB947TRGCRQ1 Visão geral
What is a serializer/deserializer (SerDes) channel? A serializer is a mixed-signal interface IC that compresses a wide parallel bus (LVCMOS color, sync, audio, control) into a high-speed serial differential link using embedded clock technology. FPD-Link III is TI's proprietary SerDes family used for automotive and industrial displays where EMI, cable weight, and connector count must be minimized. A serializer sits on the SoC/FPGA side of the harness and a deserializer on the display side, replacing 20-30 LVDS lanes with a single twisted pair.
Key features of the DS90UB947TRGCRQ1 include 3.36 Gbps forward channel, a 40 kbps to 1 Mbps back-channel return path for touch/control data, support for WUXGA (1920x1200) and 1080p60 in non-reduced-blanking mode, multi-channel I2S audio, and adaptive equalization at the deserializer side. The device supports up to 24-bit color depth and offers backward-compatible operation at WXGA and 720p over a single link.
The device uses low-voltage differential signaling (LVDS), data scrambling, and randomization to minimize EMI - critical for CISPR 25 Class 5 automotive compliance. Internal pattern generation and BIST modes allow in-system link validation without external equipment.
Typical applications include automotive infotainment head units, ADAS driver-assist displays, rear-seat entertainment, instrument clusters, and industrial HMI panels where a single twisted pair must replace wide parallel RGB harnesses.
When designing with the DS90UB947TRGCRQ1, choose a matched DS90UB948-Q1 (1080p) or DS90UH948-Q1 (4K) deserializer, plan for 100-ohm differential routing of the FPD-Link III pair, and use TI's WEBENCH FPD-Link III tool to validate cable length and pre-emphasis settings.
This page synthesizes distributor pricing, AEC-Q100 qualification evidence, drop-in package-compatible alternatives, and practical PCB layout notes not found in the manufacturer datasheet alone.
Alternativas drop-in para DS90UB947TRGCRQ1 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com DS90UB947TRGCRQ1 (mesmo formato e footprint) — diferindo em Color Depth, Function, Operating Temperature, Package.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
DS90UB947TRGCTQ1
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
DS90UH947NTRGCRQ1
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
DS90UH949TRGCRQ1
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
DS90UB947TRGCQ1
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
DS90UB948TRGCRQ1
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
DS90UB947TRGCRQ1 Especificações
| Função | OpenLDI to FPD-Link III Dual Serializer |
| Forward Channel Data Rate | Up to 3.36 Gbps |
| Back-Channel Data Rate | 40 kbps to 1 Mbps |
| Maximum Resolution | 1080p / WUXGA 1920x1200 (non-reduced blanking) |
| Color Depth | Up to 24-bit |
| Inputs | 8 (parallel RGB/YCbCr + control + audio) |
| Outputs | 2 (FPD-Link III differential pair, AC-coupled) |
| Audio Interface | I2S, multi-channel |
| Encapsulamento | VQFN-64 (RGC) 9x9 mm with exposed thermal pad |
| Contagem de pinos | 64 |
| Temperatura de operação | -40C to +105C |
| Tipo de montagem | Surface Mount |
| Nível MSL | 3 |
| Status RoHS | Compliant |
| AEC-Q100 | Qualified (automotive grade) |
Configuração de pinos do DS90UB947TRGCRQ1
| Pino 1 | RESET — Device reset input, active low |
| Pino 2 | PDB — Power-down bar input |
| Pino 3 | IDx — Device ID address select |
| Pino 4 | VCC3P3 — 3.3 V analog/digital supply |
| Pino 5 | GND — Ground reference |
| Pino 6 | DOUT+ — FPD-Link III differential output positive |
| Pino 7 | DOUT- — FPD-Link III differential output negative |
| Pino 8 | VCC1P8 — 1.8 V core supply |
| Pino 9 | TX_SCL — I2C clock to deserializer |
| Pino 10 | TX_SDA — I2C data to deserializer |
| Pino 11 | GPIO0 — General-purpose I/O 0 |
| Pino 12 | GPIO1 — General-purpose I/O 1 |
| Pino 13 | MCLK — I2S master clock input |
| Pino 14 | BCLK — I2S bit clock input |
| Pino 15 | WCLK — I2S word clock input |
| Pino 16 | DATA0 — I2S audio data input 0 |
| Pino 17 | DATA1 — I2S audio data input 1 |
| Pino 18 | DATA2 — I2S audio data input 2 |
| Pino 19 | RX_SCL — Back-channel I2C clock from deserializer |
| Pino 20 | RX_SDA — Back-channel I2C data from deserializer |
| Pino 21 | OLDI_D0N — oLDI data lane 0 negative |
| Pino 22 | OLDI_D0P — oLDI data lane 0 positive |
| Pino 23 | OLDI_D1N — oLDI data lane 1 negative |
| Pino 24 | OLDI_D1P — oLDI data lane 1 positive |
| Pino 25 | OLDI_D2N — oLDI data lane 2 negative |
| Pino 26 | OLDI_D2P — oLDI data lane 2 positive |
| Pino 27 | OLDI_D3N — oLDI data lane 3 negative |
| Pino 28 | OLDI_D3P — oLDI data lane 3 positive |
| Pino 29 | OLDI_CLKN — oLDI clock negative |
| Pino 30 | OLDI_CLKP — oLDI clock positive |
| Pino 31 | HSYNC — Horizontal sync input |
| Pino 32 | VSYNC — Vertical sync input |
| Pino 33 | DE — Data enable input |
| Pino 34 | PCLK — Pixel clock input |
| Pino 35 | GND — Ground reference |
| Pino 36 | VCC1P8 — 1.8 V core supply |
| Pino 37 | GPIO2 — General-purpose I/O 2 |
| Pino 38 | GPIO3 — General-purpose I/O 3 |
| Pino 39 | INTB — Interrupt output, active low |
| Pino 40 | CSB — Chip select bar for SPI configuration |
| Pino 41 | SCLK — SPI configuration clock |
| Pino 42 | SDI — SPI configuration data input |
| Pino 43 | SDO — SPI configuration data output |
| Pino 44 | MODE0 — Operating mode select bit 0 |
| Pino 45 | MODE1 — Operating mode select bit 1 |
| Pino 46 | VCC3P3 — 3.3 V analog/digital supply |
| Pino 47 | REFCLK — Reference clock input |
| Pino 48 | AUX_SCL — Auxiliary I2C clock |
| Pino 49 | AUX_SDA — Auxiliary I2C data |
| Pino 50 | GND — Ground reference |
| Pino 51 | RES0 — Reserved, leave floating or per datasheet |
| Pino 52 | RES1 — Reserved, leave floating or per datasheet |
| Pino 53 | RES2 — Reserved, leave floating or per datasheet |
| Pino 54 | RES3 — Reserved, leave floating or per datasheet |
| Pino 55 | RES4 — Reserved, leave floating or per datasheet |
| Pino 56 | RES5 — Reserved, leave floating or per datasheet |
| Pino 57 | RES6 — Reserved, leave floating or per datasheet |
| Pino 58 | RES7 — Reserved, leave floating or per datasheet |
| Pino 59 | GND — Ground reference |
| Pino 60 | VCC1P8 — 1.8 V core supply |
| Pino 61 | BISTEN — Built-in self-test enable |
| Pino 62 | BISTOK — Built-in self-test pass indicator |
| Pino 63 | NC — Not connected (per datasheet) |
| Pino 64 | EP — Exposed thermal pad - connect to GND |
Aplicações típicas
DS90UB947TRGCRQ1 é adequado para 6 aplicaçãos: Automotive Infotainment Head Unit, Rear-Seat Entertainment (RSE) Display, Instrument Cluster Display Link, Industrial HMI Panel (12-21 inch), Medical Imaging Diagnostic Display, Heads-Up Display (HUD) Signal Link.
Automotive Infotainment Head Unit
The DS90UB947TRGCRQ1 connects the head-unit SoC to a remote 1080p center-stack display over a single twisted pair, replacing wide parallel RGB/LVDS harnesses. Its 3.36 Gbps forward-channel rate sustains 1080p60 at 24-bit color plus multi-channel I2S audio, while the 1 Mbps back-channel carries touch and GPIO signals back to the SoC. The AEC-Q100 Grade 2 qualification and -40C to +105C range ensure reliable operation behind the dashboard where ambient temperature can exceed 85C. TI's FPD-Link III scrambling and randomization deliver CISPR 25 Class 5 EMI compliance without external shielding. Designers pair it with the DS90UB948-Q1 deserializer at the display panel.
Recomendado
Rear-Seat Entertainment (RSE) Display
For dual RSE screens fed from a single head unit, the DS90UB947TRGCRQ1's dual-output mode drives two independent display channels over separate twisted pairs from one SoC output. The 3.36 Gbps bandwidth per link is sufficient for 1080p streaming video from Blu-ray or streaming apps, while the back-channel supports remote control and seat-occupancy touch input. AEC-Q100 Grade 2 qualification and the 9x9 mm VQFN-64 footprint enable placement in confined seat-back modules. Cable lengths up to 7 m at 1080p are validated by TI's WEBENCH FPD-Link III tool without external equalization.
Recomendado
Instrument Cluster Display Link
The DS90UB947TRGCRQ1 links the cluster microcontroller to the 12.3-inch TFT cluster panel, transmitting 1920x720 WUXGA-resolution gauges and telltales at 60 Hz with sub-frame latency. Embedded-clock technology eliminates the need for a separate clock wire, simplifying the harness passing through the steering column. Automotive qualification (AEC-Q100 Grade 2) covers the extreme thermal cycling the cluster sees near HVAC vents. TI's adaptive pre-emphasis at the deserializer compensates for the connector and cable losses typical of column-mounted bundles. The exposed thermal pad (EP) on the VQFN-64 RGC package allows direct PCB heatsinking for sustained operation.
Recomendado
Industrial HMI Panel (12-21 inch)
In factory automation, the DS90UB947TRGCRQ1 connects an HMI controller SBC to a sealed-panel display 3-10 m away across noisy industrial environments. FPD-Link III's built-in scrambling, randomization, and adaptive equalization meet industrial EMI standards (EN 61000-6-2 immunity) without additional shielding. The -40C to +105C operating range supports outdoor-rated panels and proximity to motors. Industrial designers often pair it with the DS90UB948-Q1 deserializer; using the -Q1 device provides extended temperature margin at no extra cost. The 100-ohm differential pair can be routed on FR-4 without special low-loss materials.
Recomendado
Medical Imaging Diagnostic Display
For diagnostic monitors requiring uncompressed 1080p video with zero pixel jitter, the DS90UB947TRGCRQ1's clock-embedded serial link removes pixel-clock skew that plagues parallel LVDS routing across long cables. Medical-grade IEC 60601 EMI compliance is achievable using TI's recommended BCI/ESD mitigation. The 24-bit color depth preserves the full grayscale ramp needed for radiology review. Combined with the DS90UB948-Q1 deserializer, the link supports cable runs up to 7 m at full 1080p60 - sufficient for ceiling-mounted arms and boom-mounted surgical displays. The exposed pad enables adequate thermal dissipation in fanless sealed enclosures.
Recomendado
Heads-Up Display (HUD) Signal Link
The DS90UB947TRGCRQ1 routes the HUD video stream from the ADAS domain controller to the projection unit mounted in the instrument panel, often separated by 2-3 m of harness routing. FPD-Link III's single-pair topology reduces harness weight versus parallel LVDS - a critical weight-saving factor in HUD optical assemblies. AEC-Q100 Grade 2 qualification and the device's EMI hardening allow placement near the high-frequency PWM dimming drivers. The back-channel carries HUD brightness and position data back to the controller. Designers combine it with a DS90UH948-Q1 deserializer when 4K HUD imager upgrades are planned, keeping the same VQFN-64 RGC footprint.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para DS90UB947TRGCRQ1 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | DS90UB947TRGCTQ1 | DS90UH947NTRGCRQ1 | DS90UH949TRGCRQ1 | DS90UB947TRGCQ1 | DS90UB948TRGCRQ1 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | VQFN-64 (RGC) 9x9 mm | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same |
| Forward Data Rate | 3.36 Gbps | 3.36 Gbps | 7.55 Gbps | 7.55 Gbps | 3.36 Gbps | 3.36 Gbps (deserializer) |
| Role | Serializer (SoC to display) | Serializer (same) | Serializer (4K) | Serializer (4K) | Serializer (same) | Deserializer (panel side) |
| Maximum Resolution | 1080p / WUXGA 1920x1200 | 1080p / WUXGA | 4K UHD 3840x2160 | 4K UHD 3840x2160 | 1080p / WUXGA | 1080p / WUXGA (deserializes) |
| Back-Channel Rate | 40 kbps to 1 Mbps | 40 kbps to 1 Mbps | 40 kbps to 1 Mbps | 40 kbps to 1 Mbps | 40 kbps to 1 Mbps | 40 kbps to 1 Mbps |
| AEC-Q100 Grade | Grade 2 (-40C to +105C) | Grade 2 | Grade 2 | Grade 2 | Grade 2 | Grade 2 |
| Audio Interface | Multi-channel I2S | Multi-channel I2S | Multi-channel I2S | Multi-channel I2S | Multi-channel I2S | Multi-channel I2S (output) |
Principais diferenciais
- Higher bandwidth headroom for 4K upgrade paths (vs DS90UH949TRGCRQ1)
- Lower forward-channel bandwidth optimizes cost for 1080p (vs DS90UH947NTRGCRQ1)
- Serializer role on the SoC side of the link (vs DS90UB948TRGCRQ1)
Notas de projeto
Route the FPD-Link III DOUT+/DOUT- pair as a 100-ohm differential pair with intra-pair length matching to within 5 mils. Keep the pair length under 50 mm on the serializer PCB and use 50-ohm controlled impedance traces with 2x ground-pour stitching vias. Per TI SNLA224 FPD-Link III layout guide, place AC-coupling capacitors (100 nF X7R 0402) as close to the connector as possible. The exposed thermal pad (pin 64) MUST be soldered to a continuous ground plane for thermal dissipation; missing this connection causes junction temperature to exceed -40C to +105C operating range under sustained video traffic.
The DS90UB947TRGCRQ1 requires a 1.8 V core rail and a 3.3 V I/O rail with tight sequencing - VCC3P3 must reach 90% within 50 ms of VCC1P8, otherwise the device may enter an undefined state. Use an LDO with at least 200 mA capacity for VCC1P8 (typical IDD1P8 ~150 mA) and 150 mA for VCC3P3 (typical IDD3P3 ~80 mA). Bulk-decoupling: place 4.7 uF X7R on each rail adjacent to the IC, plus 100 nF NP0/C0G 0402 within 2 mm of each VCC pin. The PDB (pin 2) reset pin must be held low for at least 100 ms after VCC stabilization to ensure clean startup of the internal PLL.
Do not omit the I2C pull-up resistors on the TX_SCL/TX_SDA and RX_SCL/RX_SDA pins - the back-channel relies on external pull-ups (typically 4.7 kohm to 3.3 V) on the serializer side. Failing to do so results in intermittent link training failures that look like cable issues but are actually I2C bus contention. Also, ensure the MODE0/MODE1 (pins 44/45) are tied to the correct logic level via 10 kohm pull-up/down resistors rather than left floating - floating MODE pins may cause the device to power up in an undocumented BIST mode. Finally, do not use ferrites in series with the DOUT pair as they degrade the 3.36 Gbps signal integrity; common-mode chokes are acceptable.
Informações de conformidade
RoHS and REACH compliance per TI product page. AEC-Q100 Grade 2 qualified for automotive (-40C to +105C). Halogen-free status not specified in available data.
