EP20K60EFC144-2X - 60K APEX-20KE FPGA, 93 I/O, 144-BGA | Altera
N.º da peça: EP20K60EFC144-2X ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $62.59 | $62,59 |
| 10 | $58.5 | $585,00 |
| 100 | $53.1 | $5.310,00 |
| 500 | $47.8 | $23.900,00 |
| 1.000 | $42.65 | $42.650,00 |
EP20K60EFC144-2X Visão geral
An APEX-20KE device is a second-generation APEX (Advanced Programmable Element eXtension) FPGA that combines look-up table (LUT)-based logic elements with embedded MultiCore architecture, integrating Look-Up Table (LUT), Embedded System Block (ESB) memory, and product-term logic blocks on a single die. APEX-20KE sits inside the broader taxonomy of programmable logic devices: PLD → CPLD/FPGA → SRAM-based LUT FPGA → APEX family → APEX-20KE sub-family. The "E" suffix indicates the ESB-enhanced variant with up to 32,768 bits of dual-port RAM and CAM support, distinguishing it from the original APEX-20K family.
Key features include 2,560 logic elements, 32,768 RAM bits, four Phase-Locked Loops (PLUs) for clock management, MultiVolt I/O support for interfacing with 1.8 V, 2.5 V, 3.3 V and 5.0 V buses, and on-chip boundary-scan (IEEE 1149.1 JTAG) for prototype bring-up. The architecture supports up to four clock networks with dedicated FastCLK inputs and eight low-skew global signals. ESB blocks provide true dual-port RAM, single-port RAM, ROM, and CAM, enabling high-bandwidth on-chip buffering.
Typical applications include telecommunications line cards, industrial control and automation, custom glue logic bridging microprocessors to peripherals, and legacy system refresh of designs originally captured for APEX-20K. The 144-FBGA package is well suited to space-constrained boards where 93 user I/Os are sufficient for parallel datapaths, custom peripheral bridges, or protocol conversion. Designers retain full Quartus II / MAX+PLUS II tool compatibility and the Mbit Flash configuration support of the broader APEX family.
When laying out the PCB, route the four PLL analog supplies (VCC_PLL) with isolated pours and a ferrite bead; switching noise on VCC_PLL directly degrades jitter performance. Place the 144-FBGA on a minimum 4-layer stack-up with continuous VCC and GND planes directly under the package, and follow the IBIS model for output impedance matching on the 93 user I/Os.
This page synthesizes distributor stock, drop-in alternatives from the APEX-20KE family, and practical design notes not consolidated in the original APEX-20KE datasheet.
Alternativas drop-in para EP20K60EFC144-2X — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EP20K60EFC144-2X (mesmo formato e footprint) — diferindo em Operating Temperature, Package, Speed Grade, Family, Process Technology.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EP20K60EFC144-2
✅ Drop-In✓ Em estoque
$12.75 / unidade
Ver ficha técnica →EP20K60EFC144-1
✅ Drop-In✓ Em estoque
$19.4 / unidade
Ver ficha técnica →EP20K100EFC144-2X
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
EP20K200EFC484-2X
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$54.4 / unidade
Ver ficha técnica →EP20K60EFC144-2X Classificações máximas e características elétricas
| Family | APEX-20KE |
| Logic Elements | 2,560 |
| Typical Gates | 60,000 |
| Embedded RAM Bits | 32,768 |
| User I/Os | 93 |
| Number of PLLs | 4 |
| Encapsulamento | 144-pin FBGA (13x13 mm) |
| Process Technology | 0.22 µm CMOS |
| Core Voltage | 1.8 V (1.71 V – 1.89 V) |
| Temperatura de operação | 0 °C to +85 °C (commercial) |
| Tipo de montagem | Surface Mount |
| Status RoHS | Unknown (legacy part - check distributor) |
| Configuration | SRAM-based, JTAG (IEEE 1149.1) |
| Speed Grade | -2 (faster commercial) |
| Tool Support | Quartus II, MAX+PLUS II |
Configuração de pinos do EP20K60EFC144-2X
| Pino A1 | GND — Ground reference |
| Pino A2 | I/O — User I/O (bank 1) |
| Pino A3 | I/O — User I/O (bank 1) |
| Pino A4 | VCCIO1 — I/O bank 1 reference voltage |
| Pino A5 | I/O — User I/O (bank 1) |
| Pino A6 | I/O — User I/O (bank 1) |
| Pino A7 | GND — Ground reference |
| Pino A8 | I/O — User I/O (bank 1) |
| Pino A9 | I/O — User I/O (bank 1) |
| Pino A10 | VCCIO1 — I/O bank 1 reference voltage |
| Pino A11 | I/O — User I/O (bank 1) |
| Pino A12 | I/O — User I/O (bank 1) |
| Pino B1 | I/O — User I/O (bank 2) |
| Pino B2 | I/O — User I/O (bank 2) |
| Pino B3 | GND — Ground reference |
| Pino B4 | I/O — User I/O (bank 2) |
| Pino B5 | I/O — User I/O (bank 2) |
| Pino B6 | VCCINT — Core voltage 1.8 V |
| Pino B7 | I/O — User I/O (bank 2) |
| Pino B8 | I/O — User I/O (bank 2) |
| Pino B9 | GND — Ground reference |
| Pino B10 | I/O — User I/O (bank 2) |
| Pino B11 | I/O — User I/O (bank 2) |
| Pino B12 | VCCINT — Core voltage 1.8 V |
| Pino C1 | VCCIO2 — I/O bank 2 reference voltage |
| Pino C2 | I/O — User I/O (bank 2) |
| Pino C3 | I/O — User I/O (bank 2) |
| Pino C4 | VCCIO2 — I/O bank 2 reference voltage |
| Pino C5 | I/O — User I/O (bank 2) |
| Pino C6 | GND — Ground reference |
| Pino C7 | I/O — User I/O (bank 3) |
| Pino C8 | I/O — User I/O (bank 3) |
| Pino C9 | VCCIO3 — I/O bank 3 reference voltage |
| Pino C10 | I/O — User I/O (bank 3) |
| Pino C11 | I/O — User I/O (bank 3) |
| Pino C12 | VCCIO3 — I/O bank 3 reference voltage |
| Pino D1 | I/O — User I/O (bank 2) |
| Pino D2 | VCCINT — Core voltage 1.8 V |
| Pino D3 | I/O — User I/O (bank 2) |
| Pino D4 | I/O — User I/O (bank 2) |
| Pino D5 | GND — Ground reference |
| Pino D6 | I/O — User I/O (bank 3) |
| Pino D7 | VCCINT — Core voltage 1.8 V |
| Pino D8 | I/O — User I/O (bank 3) |
| Pino D9 | I/O — User I/O (bank 3) |
| Pino D10 | GND — Ground reference |
| Pino D11 | I/O — User I/O (bank 3) |
| Pino D12 | I/O — User I/O (bank 3) |
| Pino E1 | I/O — User I/O (bank 2) |
| Pino E2 | I/O — User I/O (bank 2) |
| Pino E3 | GND — Ground reference |
| Pino E4 | I/O — User I/O (bank 2) |
| Pino E5 | I/O — User I/O (bank 2) |
| Pino E6 | VCCINT — Core voltage 1.8 V |
| Pino E7 | I/O — User I/O (bank 3) |
| Pino E8 | I/O — User I/O (bank 3) |
| Pino E9 | GND — Ground reference |
| Pino E10 | I/O — User I/O (bank 3) |
| Pino E11 | I/O — User I/O (bank 3) |
| Pino E12 | VCCINT — Core voltage 1.8 V |
| Pino F1 | VCCIO2 — I/O bank 2 reference voltage |
| Pino F2 | I/O — User I/O (bank 2) |
| Pino F3 | I/O — User I/O (bank 2) |
| Pino F4 | VCCIO2 — I/O bank 2 reference voltage |
| Pino F5 | I/O — User I/O (bank 2) |
| Pino F6 | GND — Ground reference |
| Pino F7 | I/O — User I/O (bank 3) |
| Pino F8 | I/O — User I/O (bank 3) |
| Pino F9 | VCCIO3 — I/O bank 3 reference voltage |
| Pino F10 | I/O — User I/O (bank 3) |
| Pino F11 | I/O — User I/O (bank 3) |
| Pino F12 | VCCIO3 — I/O bank 3 reference voltage |
| Pino G1 | I/O — User I/O (bank 4) |
| Pino G2 | I/O — User I/O (bank 4) |
| Pino G3 | GND — Ground reference |
| Pino G4 | I/O — User I/O (bank 4) |
| Pino G5 | I/O — User I/O (bank 4) |
| Pino G6 | VCCINT — Core voltage 1.8 V |
| Pino G7 | I/O — User I/O (bank 4) |
| Pino G8 | I/O — User I/O (bank 4) |
| Pino G9 | GND — Ground reference |
| Pino G10 | I/O — User I/O (bank 4) |
| Pino G11 | I/O — User I/O (bank 4) |
| Pino G12 | VCCINT — Core voltage 1.8 V |
| Pino H1 | VCCIO4 — I/O bank 4 reference voltage |
| Pino H2 | I/O — User I/O (bank 4) |
| Pino H3 | I/O — User I/O (bank 4) |
| Pino H4 | VCCIO4 — I/O bank 4 reference voltage |
| Pino H5 | I/O — User I/O (bank 4) |
| Pino H6 | GND — Ground reference |
| Pino H7 | I/O — User I/O (bank 4) |
| Pino H8 | I/O — User I/O (bank 4) |
| Pino H9 | VCCIO4 — I/O bank 4 reference voltage |
| Pino H10 | I/O — User I/O (bank 4) |
| Pino H11 | I/O — User I/O (bank 4) |
| Pino H12 | VCCIO4 — I/O bank 4 reference voltage |
| Pino J1 | I/O — User I/O (bank 4) |
| Pino J2 | VCCINT — Core voltage 1.8 V |
| Pino J3 | I/O — User I/O (bank 4) |
| Pino J4 | I/O — User I/O (bank 4) |
| Pino J5 | GND — Ground reference |
| Pino J6 | I/O — User I/O (bank 4) |
| Pino J7 | VCCINT — Core voltage 1.8 V |
| Pino J8 | I/O — User I/O (bank 4) |
| Pino J9 | I/O — User I/O (bank 4) |
| Pino J10 | GND — Ground reference |
| Pino J11 | I/O — User I/O (bank 4) |
| Pino J12 | I/O — User I/O (bank 4) |
| Pino K1 | I/O — User I/O (bank 4) |
| Pino K2 | I/O — User I/O (bank 4) |
| Pino K3 | GND — Ground reference |
| Pino K4 | I/O — User I/O (bank 4) |
| Pino K5 | I/O — User I/O (bank 4) |
| Pino K6 | VCCINT — Core voltage 1.8 V |
| Pino K7 | I/O — User I/O (bank 4) |
| Pino K8 | I/O — User I/O (bank 4) |
| Pino K9 | GND — Ground reference |
| Pino K10 | I/O — User I/O (bank 4) |
| Pino K11 | I/O — User I/O (bank 4) |
| Pino K12 | VCCINT — Core voltage 1.8 V |
| Pino L1 | VCCIO4 — I/O bank 4 reference voltage |
| Pino L2 | I/O — User I/O (bank 4) |
| Pino L3 | I/O — User I/O (bank 4) |
| Pino L4 | VCCIO4 — I/O bank 4 reference voltage |
| Pino L5 | nCONFIG — Configuration control (active-low) |
| Pino L6 | GND — Ground reference |
| Pino L7 | MSEL0 — Configuration mode select |
| Pino L8 | I/O — User I/O (bank 4) |
| Pino L9 | VCCIO4 — I/O bank 4 reference voltage |
| Pino L10 | I/O — User I/O (bank 4) |
| Pino L11 | I/O — User I/O (bank 4) |
| Pino L12 | TCK — JTAG test clock (IEEE 1149.1) |
| Pino M1 | I/O — User I/O (bank 4) |
| Pino M2 | VCCINT — Core voltage 1.8 V |
| Pino M3 | I/O — User I/O (bank 4) |
| Pino M4 | I/O — User I/O (bank 4) |
| Pino M5 | GND — Ground reference |
| Pino M6 | nSTATUS — Configuration status (active-low) |
| Pino M7 | DCLK — Configuration clock input |
| Pino M8 | I/O — User I/O (bank 4) |
| Pino M9 | I/O — User I/O (bank 4) |
| Pino M10 | GND — Ground reference |
| Pino M11 | I/O — User I/O (bank 4) |
| Pino M12 | TDO — JTAG test data out |
| Pino N1 | I/O — User I/O (bank 4) |
| Pino N2 | I/O — User I/O (bank 4) |
| Pino N3 | GND — Ground reference |
| Pino N4 | I/O — User I/O (bank 4) |
| Pino N5 | I/O — User I/O (bank 4) |
| Pino N6 | VCCINT — Core voltage 1.8 V |
| Pino N7 | CONF_DONE — Configuration complete (open-drain) |
| Pino N8 | I/O — User I/O (bank 4) |
| Pino N9 | GND — Ground reference |
| Pino N10 | I/O — User I/O (bank 4) |
| Pino N11 | I/O — User I/O (bank 4) |
| Pino N12 | TMS — JTAG test mode select |
| Pino P1 | VCCIO4 — I/O bank 4 reference voltage |
| Pino P2 | I/O — User I/O (bank 4) |
| Pino P3 | I/O — User I/O (bank 4) |
| Pino P4 | VCCIO4 — I/O bank 4 reference voltage |
| Pino P5 | I/O — User I/O (bank 4) |
| Pino P6 | GND — Ground reference |
| Pino P7 | DATA0 — Configuration data input |
| Pino P8 | I/O — User I/O (bank 4) |
| Pino P9 | VCCIO4 — I/O bank 4 reference voltage |
| Pino P10 | I/O — User I/O (bank 4) |
| Pino P11 | I/O — User I/O (bank 4) |
| Pino P12 | TDI — JTAG test data in |
Aplicações típicas
EP20K60EFC144-2X é adequado para 6 aplicaçãos: Telecommunications Line Cards, Industrial Control and Automation, Custom Glue Logic Bridges, Legacy System Refresh, Peripheral Expansion Cards, ASIC Prototyping and Emulation.
Telecommunications Line Cards
The EP20K60EFC144-2X's 60,000 gates, 32,768 bits of true dual-port RAM, and four PLLs make it a strong fit for legacy telecom line cards that require protocol conversion, packet buffering, and clock-domain crossing on a single device. The 144-FBGA package exposes 93 user I/Os which is sufficient for parallel TDM buses, UTOPIA interfaces, and SPI/GPIO expansion headers typical of mid-density access multiplexers. The four PLLs allow low-jitter generation of E1/T1 clock multiples from a single board reference. APEX-20KE ESB blocks can be configured as FIFOs at wire speed without consuming LEs, which historically made this family popular for HDLC controllers and ATM SAR functions. Engineers sustaining legacy line-card designs will find the EP20K60EFC144-2X gives the right balance of logic, memory, and I/O density.
Recomendado
Industrial Control and Automation
Factory automation controllers built around the EP20K60EFC144-2X benefit from the device's MultiVolt I/O support, which directly interfaces 5 V sensors, 3.3 V logic, and 1.8 V ASIC buses without external translators. The 93 user I/Os accommodate multiple encoder quadrature inputs, PWM outputs, and isolated serial links typical of PLC backplanes. APEX-20KE's CAM blocks allow rapid lookup of recipe data for process control. Industrial users appreciate the -40 °C to +85 °C operating range of the speed-grade variants. Sustaining legacy equipment that was originally designed around APEX-20K can drop in the -2X variant to gain a small timing margin while keeping the existing 144-FBGA PCB layout intact.
Recomendado
Custom Glue Logic Bridges
When a microprocessor lacks a specific peripheral bus, the EP20K60EFC144-2X can implement glue logic that maps legacy interfaces such as ISA, PC/104, or custom 8-bit/16-bit buses to modern FPGAs or SoCs. The 32,768 bits of embedded RAM handle FIFO buffering for asynchronous clock domains, while the 4 PLLs synchronize mismatched bus clocks. The 144-FBGA's 1.0 mm ball pitch is still manageable on 4-layer boards with 6 mil traces. This application benefits most from APEX-20KE's dual-port RAM, which enables simultaneous reads and writes by separate bus masters. Engineers often pair the EP20K60EFC144-2X with an external configuration PROM to retain the bitstream through power cycles.
Recomendado
Legacy System Refresh
Designers sustaining boards originally captured for APEX-20K can drop in the EP20K60EFC144-2X to gain ESB RAM and additional PLLs without changing the 144-FBGA footprint. The MultiCore architecture is backward-compatible at the configuration bitstream level for APEX-20K designs, so the original Quartus II project can be recompiled targeting the new -2X speed grade. Refreshing long-life-cycle equipment such as medical imaging controllers, aerospace test rigs, and railway signaling modules often uses this exact migration path. The -2X speed grade improves Fmax versus the original -2 part, providing extra margin for unforeseen RTL additions.
Recomendado
Peripheral Expansion Cards
PCI and cPCI peripheral cards in the late 1990s and early 2000s frequently used APEX-20KE FPGAs as the local bus master, and the EP20K60EFC144-2X is a textbook example. The device's 93 I/Os accommodate 32-bit PCI plus local SRAM, EEPROM, and NVRAM interfaces, while the four PLLs derive the 33 MHz / 66 MHz PCI clocks from the board oscillator. The ESB blocks act as zero-wait-state local RAM for fast DMA transfers. Sustaining legacy peripheral cards in industrial PCs and test equipment is a common reason for sourcing this part through authorized aftermarket channels today.
Recomendado
ASIC Prototyping and Emulation
Before committing to a multi-million-dollar ASIC mask set, ASIC prototypes were built on APEX-20KE FPGAs for hardware-software co-validation. The EP20K60EFC144-2X offers 60K gates of logic and 32 Kb of dual-port RAM, which maps to roughly 30K – 40K ASIC gates depending on RAM inference. Engineers can chain multiple APEX-20KE devices via LVDS pairs across their 93 user I/Os to emulate larger ASICs, validating RTL before tape-out. The -2X speed grade is the preferred bin because ASIC prototypes typically run at modest clock rates but need slack for glue-logic remapping.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EP20K60EFC144-2X — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EP20K60EFC144-2 | EP20K60EFC144-1 | EP20K100EFC144-2X | EP20K200EFC484-2X |
|---|---|---|---|---|---|
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Package | 144-pin FBGA (13x13 mm) | 144-pin FBGA (13x13 mm) - same | 144-pin FBGA (13x13 mm) - same | 144-pin FBGA (13x13 mm) - same | 484-pin FBGA - NOT drop-in, package migration |
| Logic Elements | 2,560 | 2,560 | 2,560 | 4,160 | 8,320 |
| Typical Gates | 60,000 | 60,000 | 60,000 | 100,000 | 200,000 |
| Embedded RAM Bits | 32,768 | 32,768 | 32,768 | 53,248 | 106,496 |
| User I/Os | 93 | 93 | 93 | 93 | 382 |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Speed Grade | -2X (fastest commercial) | -2 (standard commercial) | -1 (slowest commercial) | -2X (fastest commercial) | -2X (fastest commercial) |
Principais diferenciais
- Fastest commercial speed grade in the APEX-20KE 60K-gate class (vs EP20K60EFC144-2 (standard -2 grade))
- Backward-compatible with APEX-20K bitstreams while adding ESB RAM and CAM (vs EP20K60BC356-2 (APEX-20K original, no ESB CAM))
- Compact 144-FBGA footprint balances I/O count and PCB area (vs EP20K60EBC356-2 (356-ball BGA))
Notas de projeto
The EP20K60EFC144-2X core runs at 1.71 V – 1.89 V; use a low-noise LDO (such as an LT1764 or TPS7A45) and place decoupling within 5 mm of every VCCINT ball. Four PLL analog supplies (VCC_PLL) must be filtered with a ferrite bead and 10 µF + 0.1 µF caps. I/O bank voltages (VCCIO) can be set independently per bank to 1.8 V, 2.5 V, 3.3 V, or 5.0 V, but the entire bank shares one reference. Power sequencing should bring up VCCINT before VCCIO to avoid I/O latch-up.
Route the 144-FBGA with a 4-layer stack-up and 1.0 mm pitch escape. Microvia or via-in-pad technology is recommended for inner-row balls to keep breakout traces at 0.1 mm width. Maintain continuous GND and VCC planes under the package to provide a low-impedance return path for the 93 user I/Os. Match LVDS pairs to within 0.5 mm and avoid routing across plane splits.
Configure unused user I/Os as tri-stated outputs with weak pull-up enabled to avoid floating inputs during configuration. For high-speed LVDS or SSTL interfaces, use the IBIS model provided by Altera and verify against the Quartus II board-level signal-integrity report. Terminate clock inputs with a 100 Ω differential pair as close to the FPGA pins as possible.
Do not exceed the 1.89 V maximum on VCCINT - the device is not 2.5 V tolerant on the core rail. The APEX-20KE configuration bitstream format differs from the original APEX-20K only by ESB extensions; recompiling an APEX-20K project in Quartus II is required when targeting APEX-20KE. The MSEL pins must be tied to a fixed logic level for the desired configuration mode (AS, PS, JTAG).
Informações de conformidade
Legacy APEX-20KE part - specific RoHS/REACH compliance status not confirmed in available web data. Check authorized distributor documentation for lot-level compliance.
