EP20K60EFC144-2X - 60K APEX-20KE FPGA, 93 I/O, 144-BGA | Altera
부품 번호: EP20K60EFC144-2X ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $62.59 | $62.59 |
| 10 | $58.5 | $585.00 |
| 100 | $53.1 | $5,310.00 |
| 500 | $47.8 | $23,900.00 |
| 1,000 | $42.65 | $42,650.00 |
EP20K60EFC144-2X 개요
An APEX-20KE device is a second-generation APEX (Advanced Programmable Element eXtension) FPGA that combines look-up table (LUT)-based logic elements with embedded MultiCore architecture, integrating Look-Up Table (LUT), Embedded System Block (ESB) memory, and product-term logic blocks on a single die. APEX-20KE sits inside the broader taxonomy of programmable logic devices: PLD → CPLD/FPGA → SRAM-based LUT FPGA → APEX family → APEX-20KE sub-family. The "E" suffix indicates the ESB-enhanced variant with up to 32,768 bits of dual-port RAM and CAM support, distinguishing it from the original APEX-20K family.
Key features include 2,560 logic elements, 32,768 RAM bits, four Phase-Locked Loops (PLUs) for clock management, MultiVolt I/O support for interfacing with 1.8 V, 2.5 V, 3.3 V and 5.0 V buses, and on-chip boundary-scan (IEEE 1149.1 JTAG) for prototype bring-up. The architecture supports up to four clock networks with dedicated FastCLK inputs and eight low-skew global signals. ESB blocks provide true dual-port RAM, single-port RAM, ROM, and CAM, enabling high-bandwidth on-chip buffering.
Typical applications include telecommunications line cards, industrial control and automation, custom glue logic bridging microprocessors to peripherals, and legacy system refresh of designs originally captured for APEX-20K. The 144-FBGA package is well suited to space-constrained boards where 93 user I/Os are sufficient for parallel datapaths, custom peripheral bridges, or protocol conversion. Designers retain full Quartus II / MAX+PLUS II tool compatibility and the Mbit Flash configuration support of the broader APEX family.
When laying out the PCB, route the four PLL analog supplies (VCC_PLL) with isolated pours and a ferrite bead; switching noise on VCC_PLL directly degrades jitter performance. Place the 144-FBGA on a minimum 4-layer stack-up with continuous VCC and GND planes directly under the package, and follow the IBIS model for output impedance matching on the 93 user I/Os.
This page synthesizes distributor stock, drop-in alternatives from the APEX-20KE family, and practical design notes not consolidated in the original APEX-20KE datasheet.
드롭인 대체품: EP20K60EFC144-2X — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP20K60EFC144-2X (동일 폼 팩터 및 풋프린트) — 차이점: Operating Temperature, Package, Speed Grade, Family, Process Technology.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP20K60EFC144-2
✅ 드롭인✓ 재고 있음
$12.75 / 개
데이터시트 보기 →EP20K60EFC144-1
✅ 드롭인✓ 재고 있음
$19.4 / 개
데이터시트 보기 →EP20K100EFC144-2X
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
EP20K200EFC484-2X
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$54.4 / 개
데이터시트 보기 →EP20K60EFC144-2X 최대 정격 & 전기적 특성
| Family | APEX-20KE |
| Logic Elements | 2,560 |
| Typical Gates | 60,000 |
| Embedded RAM Bits | 32,768 |
| User I/Os | 93 |
| Number of PLLs | 4 |
| 패키지 | 144-pin FBGA (13x13 mm) |
| Process Technology | 0.22 µm CMOS |
| Core Voltage | 1.8 V (1.71 V – 1.89 V) |
| 동작 온도 | 0 °C to +85 °C (commercial) |
| 실장 유형 | Surface Mount |
| RoHS 상태 | Unknown (legacy part - check distributor) |
| Configuration | SRAM-based, JTAG (IEEE 1149.1) |
| Speed Grade | -2 (faster commercial) |
| Tool Support | Quartus II, MAX+PLUS II |
EP20K60EFC144-2X 핀 구성
| 핀 A1 | GND — Ground reference |
| 핀 A2 | I/O — User I/O (bank 1) |
| 핀 A3 | I/O — User I/O (bank 1) |
| 핀 A4 | VCCIO1 — I/O bank 1 reference voltage |
| 핀 A5 | I/O — User I/O (bank 1) |
| 핀 A6 | I/O — User I/O (bank 1) |
| 핀 A7 | GND — Ground reference |
| 핀 A8 | I/O — User I/O (bank 1) |
| 핀 A9 | I/O — User I/O (bank 1) |
| 핀 A10 | VCCIO1 — I/O bank 1 reference voltage |
| 핀 A11 | I/O — User I/O (bank 1) |
| 핀 A12 | I/O — User I/O (bank 1) |
| 핀 B1 | I/O — User I/O (bank 2) |
| 핀 B2 | I/O — User I/O (bank 2) |
| 핀 B3 | GND — Ground reference |
| 핀 B4 | I/O — User I/O (bank 2) |
| 핀 B5 | I/O — User I/O (bank 2) |
| 핀 B6 | VCCINT — Core voltage 1.8 V |
| 핀 B7 | I/O — User I/O (bank 2) |
| 핀 B8 | I/O — User I/O (bank 2) |
| 핀 B9 | GND — Ground reference |
| 핀 B10 | I/O — User I/O (bank 2) |
| 핀 B11 | I/O — User I/O (bank 2) |
| 핀 B12 | VCCINT — Core voltage 1.8 V |
| 핀 C1 | VCCIO2 — I/O bank 2 reference voltage |
| 핀 C2 | I/O — User I/O (bank 2) |
| 핀 C3 | I/O — User I/O (bank 2) |
| 핀 C4 | VCCIO2 — I/O bank 2 reference voltage |
| 핀 C5 | I/O — User I/O (bank 2) |
| 핀 C6 | GND — Ground reference |
| 핀 C7 | I/O — User I/O (bank 3) |
| 핀 C8 | I/O — User I/O (bank 3) |
| 핀 C9 | VCCIO3 — I/O bank 3 reference voltage |
| 핀 C10 | I/O — User I/O (bank 3) |
| 핀 C11 | I/O — User I/O (bank 3) |
| 핀 C12 | VCCIO3 — I/O bank 3 reference voltage |
| 핀 D1 | I/O — User I/O (bank 2) |
| 핀 D2 | VCCINT — Core voltage 1.8 V |
| 핀 D3 | I/O — User I/O (bank 2) |
| 핀 D4 | I/O — User I/O (bank 2) |
| 핀 D5 | GND — Ground reference |
| 핀 D6 | I/O — User I/O (bank 3) |
| 핀 D7 | VCCINT — Core voltage 1.8 V |
| 핀 D8 | I/O — User I/O (bank 3) |
| 핀 D9 | I/O — User I/O (bank 3) |
| 핀 D10 | GND — Ground reference |
| 핀 D11 | I/O — User I/O (bank 3) |
| 핀 D12 | I/O — User I/O (bank 3) |
| 핀 E1 | I/O — User I/O (bank 2) |
| 핀 E2 | I/O — User I/O (bank 2) |
| 핀 E3 | GND — Ground reference |
| 핀 E4 | I/O — User I/O (bank 2) |
| 핀 E5 | I/O — User I/O (bank 2) |
| 핀 E6 | VCCINT — Core voltage 1.8 V |
| 핀 E7 | I/O — User I/O (bank 3) |
| 핀 E8 | I/O — User I/O (bank 3) |
| 핀 E9 | GND — Ground reference |
| 핀 E10 | I/O — User I/O (bank 3) |
| 핀 E11 | I/O — User I/O (bank 3) |
| 핀 E12 | VCCINT — Core voltage 1.8 V |
| 핀 F1 | VCCIO2 — I/O bank 2 reference voltage |
| 핀 F2 | I/O — User I/O (bank 2) |
| 핀 F3 | I/O — User I/O (bank 2) |
| 핀 F4 | VCCIO2 — I/O bank 2 reference voltage |
| 핀 F5 | I/O — User I/O (bank 2) |
| 핀 F6 | GND — Ground reference |
| 핀 F7 | I/O — User I/O (bank 3) |
| 핀 F8 | I/O — User I/O (bank 3) |
| 핀 F9 | VCCIO3 — I/O bank 3 reference voltage |
| 핀 F10 | I/O — User I/O (bank 3) |
| 핀 F11 | I/O — User I/O (bank 3) |
| 핀 F12 | VCCIO3 — I/O bank 3 reference voltage |
| 핀 G1 | I/O — User I/O (bank 4) |
| 핀 G2 | I/O — User I/O (bank 4) |
| 핀 G3 | GND — Ground reference |
| 핀 G4 | I/O — User I/O (bank 4) |
| 핀 G5 | I/O — User I/O (bank 4) |
| 핀 G6 | VCCINT — Core voltage 1.8 V |
| 핀 G7 | I/O — User I/O (bank 4) |
| 핀 G8 | I/O — User I/O (bank 4) |
| 핀 G9 | GND — Ground reference |
| 핀 G10 | I/O — User I/O (bank 4) |
| 핀 G11 | I/O — User I/O (bank 4) |
| 핀 G12 | VCCINT — Core voltage 1.8 V |
| 핀 H1 | VCCIO4 — I/O bank 4 reference voltage |
| 핀 H2 | I/O — User I/O (bank 4) |
| 핀 H3 | I/O — User I/O (bank 4) |
| 핀 H4 | VCCIO4 — I/O bank 4 reference voltage |
| 핀 H5 | I/O — User I/O (bank 4) |
| 핀 H6 | GND — Ground reference |
| 핀 H7 | I/O — User I/O (bank 4) |
| 핀 H8 | I/O — User I/O (bank 4) |
| 핀 H9 | VCCIO4 — I/O bank 4 reference voltage |
| 핀 H10 | I/O — User I/O (bank 4) |
| 핀 H11 | I/O — User I/O (bank 4) |
| 핀 H12 | VCCIO4 — I/O bank 4 reference voltage |
| 핀 J1 | I/O — User I/O (bank 4) |
| 핀 J2 | VCCINT — Core voltage 1.8 V |
| 핀 J3 | I/O — User I/O (bank 4) |
| 핀 J4 | I/O — User I/O (bank 4) |
| 핀 J5 | GND — Ground reference |
| 핀 J6 | I/O — User I/O (bank 4) |
| 핀 J7 | VCCINT — Core voltage 1.8 V |
| 핀 J8 | I/O — User I/O (bank 4) |
| 핀 J9 | I/O — User I/O (bank 4) |
| 핀 J10 | GND — Ground reference |
| 핀 J11 | I/O — User I/O (bank 4) |
| 핀 J12 | I/O — User I/O (bank 4) |
| 핀 K1 | I/O — User I/O (bank 4) |
| 핀 K2 | I/O — User I/O (bank 4) |
| 핀 K3 | GND — Ground reference |
| 핀 K4 | I/O — User I/O (bank 4) |
| 핀 K5 | I/O — User I/O (bank 4) |
| 핀 K6 | VCCINT — Core voltage 1.8 V |
| 핀 K7 | I/O — User I/O (bank 4) |
| 핀 K8 | I/O — User I/O (bank 4) |
| 핀 K9 | GND — Ground reference |
| 핀 K10 | I/O — User I/O (bank 4) |
| 핀 K11 | I/O — User I/O (bank 4) |
| 핀 K12 | VCCINT — Core voltage 1.8 V |
| 핀 L1 | VCCIO4 — I/O bank 4 reference voltage |
| 핀 L2 | I/O — User I/O (bank 4) |
| 핀 L3 | I/O — User I/O (bank 4) |
| 핀 L4 | VCCIO4 — I/O bank 4 reference voltage |
| 핀 L5 | nCONFIG — Configuration control (active-low) |
| 핀 L6 | GND — Ground reference |
| 핀 L7 | MSEL0 — Configuration mode select |
| 핀 L8 | I/O — User I/O (bank 4) |
| 핀 L9 | VCCIO4 — I/O bank 4 reference voltage |
| 핀 L10 | I/O — User I/O (bank 4) |
| 핀 L11 | I/O — User I/O (bank 4) |
| 핀 L12 | TCK — JTAG test clock (IEEE 1149.1) |
| 핀 M1 | I/O — User I/O (bank 4) |
| 핀 M2 | VCCINT — Core voltage 1.8 V |
| 핀 M3 | I/O — User I/O (bank 4) |
| 핀 M4 | I/O — User I/O (bank 4) |
| 핀 M5 | GND — Ground reference |
| 핀 M6 | nSTATUS — Configuration status (active-low) |
| 핀 M7 | DCLK — Configuration clock input |
| 핀 M8 | I/O — User I/O (bank 4) |
| 핀 M9 | I/O — User I/O (bank 4) |
| 핀 M10 | GND — Ground reference |
| 핀 M11 | I/O — User I/O (bank 4) |
| 핀 M12 | TDO — JTAG test data out |
| 핀 N1 | I/O — User I/O (bank 4) |
| 핀 N2 | I/O — User I/O (bank 4) |
| 핀 N3 | GND — Ground reference |
| 핀 N4 | I/O — User I/O (bank 4) |
| 핀 N5 | I/O — User I/O (bank 4) |
| 핀 N6 | VCCINT — Core voltage 1.8 V |
| 핀 N7 | CONF_DONE — Configuration complete (open-drain) |
| 핀 N8 | I/O — User I/O (bank 4) |
| 핀 N9 | GND — Ground reference |
| 핀 N10 | I/O — User I/O (bank 4) |
| 핀 N11 | I/O — User I/O (bank 4) |
| 핀 N12 | TMS — JTAG test mode select |
| 핀 P1 | VCCIO4 — I/O bank 4 reference voltage |
| 핀 P2 | I/O — User I/O (bank 4) |
| 핀 P3 | I/O — User I/O (bank 4) |
| 핀 P4 | VCCIO4 — I/O bank 4 reference voltage |
| 핀 P5 | I/O — User I/O (bank 4) |
| 핀 P6 | GND — Ground reference |
| 핀 P7 | DATA0 — Configuration data input |
| 핀 P8 | I/O — User I/O (bank 4) |
| 핀 P9 | VCCIO4 — I/O bank 4 reference voltage |
| 핀 P10 | I/O — User I/O (bank 4) |
| 핀 P11 | I/O — User I/O (bank 4) |
| 핀 P12 | TDI — JTAG test data in |
일반적인 애플리케이션
EP20K60EFC144-2X 적합 용도: 6 애플리케이션s: Telecommunications Line Cards, Industrial Control and Automation, Custom Glue Logic Bridges, Legacy System Refresh, Peripheral Expansion Cards, ASIC Prototyping and Emulation.
Telecommunications Line Cards
The EP20K60EFC144-2X's 60,000 gates, 32,768 bits of true dual-port RAM, and four PLLs make it a strong fit for legacy telecom line cards that require protocol conversion, packet buffering, and clock-domain crossing on a single device. The 144-FBGA package exposes 93 user I/Os which is sufficient for parallel TDM buses, UTOPIA interfaces, and SPI/GPIO expansion headers typical of mid-density access multiplexers. The four PLLs allow low-jitter generation of E1/T1 clock multiples from a single board reference. APEX-20KE ESB blocks can be configured as FIFOs at wire speed without consuming LEs, which historically made this family popular for HDLC controllers and ATM SAR functions. Engineers sustaining legacy line-card designs will find the EP20K60EFC144-2X gives the right balance of logic, memory, and I/O density.
추천
Industrial Control and Automation
Factory automation controllers built around the EP20K60EFC144-2X benefit from the device's MultiVolt I/O support, which directly interfaces 5 V sensors, 3.3 V logic, and 1.8 V ASIC buses without external translators. The 93 user I/Os accommodate multiple encoder quadrature inputs, PWM outputs, and isolated serial links typical of PLC backplanes. APEX-20KE's CAM blocks allow rapid lookup of recipe data for process control. Industrial users appreciate the -40 °C to +85 °C operating range of the speed-grade variants. Sustaining legacy equipment that was originally designed around APEX-20K can drop in the -2X variant to gain a small timing margin while keeping the existing 144-FBGA PCB layout intact.
추천
Custom Glue Logic Bridges
When a microprocessor lacks a specific peripheral bus, the EP20K60EFC144-2X can implement glue logic that maps legacy interfaces such as ISA, PC/104, or custom 8-bit/16-bit buses to modern FPGAs or SoCs. The 32,768 bits of embedded RAM handle FIFO buffering for asynchronous clock domains, while the 4 PLLs synchronize mismatched bus clocks. The 144-FBGA's 1.0 mm ball pitch is still manageable on 4-layer boards with 6 mil traces. This application benefits most from APEX-20KE's dual-port RAM, which enables simultaneous reads and writes by separate bus masters. Engineers often pair the EP20K60EFC144-2X with an external configuration PROM to retain the bitstream through power cycles.
추천
Legacy System Refresh
Designers sustaining boards originally captured for APEX-20K can drop in the EP20K60EFC144-2X to gain ESB RAM and additional PLLs without changing the 144-FBGA footprint. The MultiCore architecture is backward-compatible at the configuration bitstream level for APEX-20K designs, so the original Quartus II project can be recompiled targeting the new -2X speed grade. Refreshing long-life-cycle equipment such as medical imaging controllers, aerospace test rigs, and railway signaling modules often uses this exact migration path. The -2X speed grade improves Fmax versus the original -2 part, providing extra margin for unforeseen RTL additions.
추천
Peripheral Expansion Cards
PCI and cPCI peripheral cards in the late 1990s and early 2000s frequently used APEX-20KE FPGAs as the local bus master, and the EP20K60EFC144-2X is a textbook example. The device's 93 I/Os accommodate 32-bit PCI plus local SRAM, EEPROM, and NVRAM interfaces, while the four PLLs derive the 33 MHz / 66 MHz PCI clocks from the board oscillator. The ESB blocks act as zero-wait-state local RAM for fast DMA transfers. Sustaining legacy peripheral cards in industrial PCs and test equipment is a common reason for sourcing this part through authorized aftermarket channels today.
추천
ASIC Prototyping and Emulation
Before committing to a multi-million-dollar ASIC mask set, ASIC prototypes were built on APEX-20KE FPGAs for hardware-software co-validation. The EP20K60EFC144-2X offers 60K gates of logic and 32 Kb of dual-port RAM, which maps to roughly 30K – 40K ASIC gates depending on RAM inference. Engineers can chain multiple APEX-20KE devices via LVDS pairs across their 93 user I/Os to emulate larger ASICs, validating RTL before tape-out. The -2X speed grade is the preferred bin because ASIC prototypes typically run at modest clock rates but need slack for glue-logic remapping.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP20K60EFC144-2X — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP20K60EFC144-2 | EP20K60EFC144-1 | EP20K100EFC144-2X | EP20K200EFC484-2X |
|---|---|---|---|---|---|
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Package | 144-pin FBGA (13x13 mm) | 144-pin FBGA (13x13 mm) - same | 144-pin FBGA (13x13 mm) - same | 144-pin FBGA (13x13 mm) - same | 484-pin FBGA - NOT drop-in, package migration |
| Logic Elements | 2,560 | 2,560 | 2,560 | 4,160 | 8,320 |
| Typical Gates | 60,000 | 60,000 | 60,000 | 100,000 | 200,000 |
| Embedded RAM Bits | 32,768 | 32,768 | 32,768 | 53,248 | 106,496 |
| User I/Os | 93 | 93 | 93 | 93 | 382 |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Speed Grade | -2X (fastest commercial) | -2 (standard commercial) | -1 (slowest commercial) | -2X (fastest commercial) | -2X (fastest commercial) |
주요 차별점
- Fastest commercial speed grade in the APEX-20KE 60K-gate class (vs EP20K60EFC144-2 (standard -2 grade))
- Backward-compatible with APEX-20K bitstreams while adding ESB RAM and CAM (vs EP20K60BC356-2 (APEX-20K original, no ESB CAM))
- Compact 144-FBGA footprint balances I/O count and PCB area (vs EP20K60EBC356-2 (356-ball BGA))
설계 노트
The EP20K60EFC144-2X core runs at 1.71 V – 1.89 V; use a low-noise LDO (such as an LT1764 or TPS7A45) and place decoupling within 5 mm of every VCCINT ball. Four PLL analog supplies (VCC_PLL) must be filtered with a ferrite bead and 10 µF + 0.1 µF caps. I/O bank voltages (VCCIO) can be set independently per bank to 1.8 V, 2.5 V, 3.3 V, or 5.0 V, but the entire bank shares one reference. Power sequencing should bring up VCCINT before VCCIO to avoid I/O latch-up.
Route the 144-FBGA with a 4-layer stack-up and 1.0 mm pitch escape. Microvia or via-in-pad technology is recommended for inner-row balls to keep breakout traces at 0.1 mm width. Maintain continuous GND and VCC planes under the package to provide a low-impedance return path for the 93 user I/Os. Match LVDS pairs to within 0.5 mm and avoid routing across plane splits.
Configure unused user I/Os as tri-stated outputs with weak pull-up enabled to avoid floating inputs during configuration. For high-speed LVDS or SSTL interfaces, use the IBIS model provided by Altera and verify against the Quartus II board-level signal-integrity report. Terminate clock inputs with a 100 Ω differential pair as close to the FPGA pins as possible.
Do not exceed the 1.89 V maximum on VCCINT - the device is not 2.5 V tolerant on the core rail. The APEX-20KE configuration bitstream format differs from the original APEX-20K only by ESB extensions; recompiling an APEX-20K project in Quartus II is required when targeting APEX-20KE. The MSEL pins must be tied to a fixed logic level for the desired configuration mode (AS, PS, JTAG).
규정 준수 정보
Legacy APEX-20KE part - specific RoHS/REACH compliance status not confirmed in available web data. Check authorized distributor documentation for lot-level compliance.
