Altera

EPM9560ARC208-10N - MAX 9000 CPLD 560 Macro 208-RQFP | Altera

Name: EPM9560ARC208-10N - MAX 9000 CPLD 560 Macro 208-RQFP | Altera
Brand: Altera
SKU: EPM9560ARC208-10N
Price: 27.2 USD
Availability: InStock

N.º da peça: EPM9560ARC208-10N ✗ Fim de vida

Em estoque Enviado em 1 a 3 dias úteis

5 V Vdss 208-pin RQFP (PowerQuad II) Package 144.9 MHz Speed EEPROM (non-volatile) Memory

A partir de $27.2 USD / unidade

MOQ: 1 |

Preço atualizado: 2026-09-13

Preços por volume

Qtd.	Preço unitário	Total
1	$42.5	$42,50
10	$38.25	$382,50
100	$34	$3.400,00
500	$30.6	$15.300,00
1.000	$27.2	$27.200,00

ℹ️ Todos os preços estão em USD

Ver datasheet (PDF) Ver alternativas

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EPM9560ARC208-10N Visão geral

The Altera EPM9560ARC208-10N is a MAX 9000 family Complex Programmable Logic Device (CPLD) with 560 macrocells, 12,000 usable gates, 153 user I/O pins, and a 10 ns pin-to-pin propagation delay, housed in a 208-pin RQFP (PowerQuad II) package. It is a 5 V in-system-programmable EEPROM-based PLD built on Altera's third-generation MAX architecture.

A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the architectural structure of a PAL with the density and flexibility of an FPGA. CPLDs sit between simple glue logic and full FPGAs in the programmable logic hierarchy: they offer non-volatile configuration, deterministic pin-to-pin timing, and low standby power, making them ideal for address decoding, bus bridging, state machines, and interface glue. The MAX 9000 family extends this concept to 6,000-12,000 usable gates with counter speeds up to 144 MHz.

Key features of the EPM9560ARC208-10N include 560 macrocells organized in 20 LABs, 153 user I/O pins, 10 ns pin-to-pin delay, 144.9 MHz internal counter frequency, and 5 V CMOS EEPROM technology that retains configuration without an external boot device. The EEPROM-based architecture allows in-system programming (ISP) via the JTAG interface, eliminating the need for a separate configuration PROM.

The MAX 9000 architecture uses a Multiple Array MatriX (MAX) structure with product-term logic, providing predictable timing independent of routing. This deterministic timing behavior is a key advantage over SRAM-based FPGAs for safety-critical and real-time control applications where worst-case delay must be guaranteed.

Typical applications include industrial control backplanes, telecommunications line cards, PCI/ISA bus interfaces, instrumentation front-ends, and legacy system replacement where 5 V logic compatibility is required. The 208-pin RQFP package provides 153 I/O pins for wide bus interfacing.

When designing with this device, note that it is a 5 V core part and requires 5 V supply rails; level shifting is needed when interfacing with 3.3 V or lower logic. The EEPROM configuration is retained for over 20 years, but the device is now obsolete and should be designed out for new projects.

This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with a single reference for replacement and migration decisions.

Alternativas drop-in para EPM9560ARC208-10N — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.

Variantes desta série

Modelos da mesma série compatíveis como drop-in com EPM9560ARC208-10N (mesmo formato e footprint) — diferindo em Package, Operating Temperature, Usable Gates, User I/O Pins, Architecture.

EPM9480RC208-15

Intel

Package: RQFP-208

Operating Temperature: -40C to +85C (commercial)

Usable Gates: 10,000 gates